isppac-clk5620v-01t48c Lattice Semiconductor Corp., isppac-clk5620v-01t48c Datasheet - Page 21

• Manufacturer Part Number: isppac-clk5620v-01t48c
• Description: In-system Programmable, Zero-delay Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Differential HSTL and SSTL
HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory
systems. Figure 16 shows how ispClock5600 reference input should be configured for accepting these standards.
The major difference between differential and single-ended forms of these logic standards is that in the differential
case, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are
engaged and set to 50 .
Figure 16. Differential HSTL/SSTL Receiver Configuration
LVDS/Differential LVPECL
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50 . The associated REFVTT or FBKVTT pin, however, should be left unconnected. This cre-
ates a floating 100 differential termination resistance across the input terminals. The LVDS termination configura-
tion is shown in Figure 17.
Figure 17. LVDS Input Receiver Configuration
Driver
LVDS
VTT
+Signal In
-Signal In
REFVTT
REFA+
REFA-
-Signal In
+Signal In
ispClock5600
50
CLOSED
No Connect
REFVTT
50
REFA+
REFA-
21
CLOSED
ispClock5600
50
Differential
Receiver
CLOSED
ispClock5600 Family Data Sheet
50
CLOSED
Differential
Receiver