isppac81 Lattice Semiconductor Corp., isppac81 Datasheet
isppac81
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isppac81 Summary of contents
Page 1
... CAL 6 ENSPI 7 GND 8 Description The ispPAC81 is a member of the Lattice family of In-System Programmable analog circuits, digitally configured via nonvol- 2 atile E CMOS technology. Analog building blocks, called PACell™(s), replace traditional analog components such as opamps, eliminating the need for external resistors and capacitors. With no requirement for external confi ...
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... OUT (VREF = ±1%) sink OUT 10MHz bandwidth 1kHz 0V ≤ TCK, ENSPI, CAL input ≤ ≤ TDI, MTS, CS inputs ≤ 4.0mA -1.0mA OH 2 ispPAC81 Data Sheet = 17.62kHz; P Min. Typ. Max IN 250 1,000 2.5 10 100 ...
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... Although many hundreds of thousands of filter configurations are avail- able using ispPAC81, not every type will have corner frequencies available from exactly 10kHz to 75kHz, depending on the tables available from within PAC-Designer filter design tools. The general specifications given under this heading are realized using the Elliptic filter types. For more information on other types and/or frequencies not contained in the fi ...
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... Test pin. Connect to GND for proper circuit operation. Differential output pins, using two pins (e.g., OUT+ and OUT-). Complementary with respect to VREFOUT. Differential V OUT Analog supply voltage pin (5V nominal). Should be bypassed to GND with 1µF and .01µF capacitors. , 2.5V). OUT 4 ispPAC81 Data Sheet Description , where differential OUT+ ...
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... Lattice Semiconductor Part Number Description Device Family Device Number ispPAC81 Ordering Information ispPAC81-01PI ispPAC81-01SI Package Options ispPAC81 – Part Number 1 1 16-Pin PDIP 16-Pin SOIC 5 ispPAC81 Data Sheet Grade Blank = Commercial I = Industrial Package P = PDIP S = SOIC Performance Grade 01 = Standard Package 16-pin PDIP ...
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... Condition Executed in Run-Test/Idle Executed in Run-Test/Idle Automatically executed at power-up Executed on rising edge of CAL tckmin TCK tmss TMS CAL tcalmin tdoxz V OUT 6 ispPAC81 Data Sheet Min. Typ. Max. 200 ...
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... TDO float to valid delay tdov TDO valid delay tdoxz TDO valid to float delay TCK CS TDI TDO Condition tckmin tckh tckl tcss tdis tdih tdozx tdov hi-z 7 ispPAC81 Data Sheet Min. Typ. Max. 200 100 100 tcsminhi tdoxz hi-z Units ns ns ...
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... Tempco OS 35 PDIP Pkg 30 -40°C to +85° 100k -240 -120 0 120 Offset Tempco (µV/°C) 8 ispPAC81 Data Sheet PSR vs. Frequency 100k 1M 100 1k 10k Frequency (Hz) Filter Variation (3 Sigma Passband ripple variation over process < 0.20dB ...
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... Another common name for this type of filter is the Elliptic family of filters. The next set of numbers, “05” refers to the order of the filter. In the case of ispPAC81 this will always be fifth order. The next two digits signify the reflection coefficient (rf), in this case 10%, and has a direct mathematical relationship to the passband ripple magnitude of the fi ...
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... The only way to prevent this behavior would be to hold the ENSPI pin low while applying power to the device. Because this is usually impractical advised that if the ispPAC81 is used in SPI mode that it be reloaded to the desired first configuration every time power is cycled to the device and/or that the “A” configu- ration memory hold the desired “ ...
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... AN6019, Differential Signaling. Single-ended Input To connect the ispPAC81 differential input to a single-ended signal, one of the differential inputs needs to be con- nected bias, preferably VREF the DC level of the other input. Since the input voltage is defined as V The signal information is only present on one input, the other being connected to a voltage reference ...
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... Circuit designs are entered graphically and then verified, all within the PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface of the ispPAC81. A database of filter configurations is included with thousands of possible implementations to choose from. In addition, comprehensive on-line and printed documenta- tion is provided that covers all aspects of PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 2, provides access to all confi ...
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... There is also a user-positioned crosshair cursor that intersects the curves on the plot, and reads out the gain and frequency in the lower right hand corner of the plot window when activated. Figure 2. Initial PAC-Designer Schematic Design Entry Screen PAC Designer - [ispPAC81.PAC: Plot] File Edit ...
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... Included in the basic ispPAC81 Design Kit is an engineering prototype board that can be connected to the parallel port of a PC. It demonstrates proper layout techniques for the ispPAC81 and can be used in real time to check cir- cuit operation as part of the design process. Input and output connections as well as a “breadboard” circuit area are provided to speed debugging of the circuit. Figure 4. Confi ...
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... BYPASS mode to maintain compliance with the specification. The optional identification register described in IEEE 1149.1 is also included in the ispPAC81. One additional data register included in the TAP of the ispPAC81 is the Lattice defined user register. Figure 5 shows how the instruction and various data registers are placed in an ispPAC81 ...
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... Register while an external operation is performed. From the Pause state, shifting can resume by reentering the 1 1 Select-DR-Scan 0 1 Capture-DR 0 Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- ispPAC81 Data Sheet 1 Select-IR-Scan 0 1 Capture-IR 0 Shift- Exit1-IR 0 Pause- Exit2-IR 1 Update- ...
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... The ispPAC81 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and verified. For ispPAC81, the instruction word length is five bits. All ispPAC81 instructions available to users are shown in Table 5. Table 5. ispPAC81 TAP Instructions ...
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... The user register is a 96-bit shift register that contains all the user-controlled parametric data pertaining to the configuration of the ispPAC81. NOTE: Although the user register length is 96 bits, only the “A” configuration is that long. The device gain setting bits, UES bits, and security fuse bit are all part of the “A” configu- ration memory and are not stored at all in “ ...
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... It is recommended that when all serial interface operations are completed, the TAP controller be reset and left in the Test-Logic-Reset state (the power-up default) and the TCK and TMS inputs idled. This will insure the best ana- log performance possible by minimizing the effects of digital logic “feed-through.” ispPAC81 Data Sheet 19 ...
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... BSC .402 (10.21) .412 (10.46) .240 / .260 (6.10 / 6.60) .195 (4.95) MAX .125 / .135 (3.17 / 3.43) .055 /.065 (1.40 / 1.65) .015 /.022 (.38 / .56) .400 (10.16) .410 (10.41) .014 (.35) .019 (.48) .097 (2.46) .104 (2.64 .0050 (.127) .0115 (.292) 20 ispPAC81 Data Sheet .300 / .325 (7.61 / 8.25) .008 / .012 0-15 (.20 / .31) .015 (.38) MIN .0091 (.23) .0125 (.32) .024 (.61) .040 (1.02) ...