isppac81 Lattice Semiconductor Corp., isppac81 Datasheet - Page 12

• Manufacturer Part Number: isppac81
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 4. Input Common-Mode Voltage Range Limitations
Software-Based Design Environment
Design Entry Software
Designers configure the ispPAC81 and verify its performance using PAC-Designer, an easy-to-use, Microsoft Win-
dows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer
environment. Full device programming is supported using PC parallel port I/O operations and a download cable
connected to the serial programming interface of the ispPAC81. A database of filter configurations is included with
thousands of possible implementations to choose from. In addition, comprehensive on-line and printed documenta-
tion is provided that covers all aspects of PAC-Designer operation.
The PAC-Designer schematic window, shown in Figure 2, provides access to all configurable ispPAC81 elements
via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins
such as power, ground, VREF
matic window can be accessed via mouse operations as well as menu commands. When completed, configura-
tions can be saved, simulated, and downloaded to devices.
PAC-Designer operation can be automated and extended by using custom-designed Visual Basic™ programs that
set the interconnections and the parameters of ispPAC products. More information on this and other topics is
included in the on-line documentation as well as the PAC-Designer Getting Started Manual.
Design Simulation Capability
A powerful feature of PAC-Designer is its simulation capability, enabling quick and accurate verification of circuit
operation and performance. Once a circuit is configured via the interactive design process, gain and phase
response between any input and output can then be determined. This function is part of the simulator capability
which derives a transfer equation between the two points and then sweeps it over the user-specified frequency
range. Figure 3 shows a typical screen plot of the gain/phase simulator. In it are the input to output response
curves of an Elliptical and a Butterworth response stored in configuration A and B respectively. These are the two
options specified in the design screen window shown in Figure 2.
*Peak input voltage for guaranteed performance at a given gain setting.
1.000
1.100
1.200
1.300
1.400
1.500
1.600
1.700
1.800
1.900
2.000
2.100
2.200
2.300
2.400
2.426
2.500
V
CM-
OUT
, and the serial digital interface are omitted for clarity. Any element in the sche-
4.000
3.900
3.800
3.700
3.600
3.500
3.400
3.300
3.200
3.100
3.000
2.900
2.800
2.700
2.600
2.574
2.500
V
Input Voltage Magnitude (Volts-Peak)
CM+
3.000*
0.557
0.728
0.899
1.071
1.242
1.413
1.584
1.756
1.927
2.098
2.270
2.441
2.612
2.783
2.955
3.126
G=1
12
1.500*
0.278
0.364
0.450
0.535
0.621
0.707
0.792
0.878
0.964
1.049
1.135
1.220
1.306
1.392
1.477
1.563
G=2
0.600*
0.111
0.146
0.180
0.214
0.248
0.283
0.317
0.351
0.385
0.420
0.454
0.488
0.522
0.557
0.591
0.625
G=5
0.300*
G=10
0.056
0.073
0.090
0.107
0.124
0.141
0.158
0.176
0.193
0.210
0.227
0.244
0.261
0.278
0.295
0.313
ispPAC81 Data Sheet