isppac81 Lattice Semiconductor Corp., isppac81 Datasheet - Page 15

• Manufacturer Part Number: isppac81
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispPAC81 Data Sheet
IEEE Standard 1149.1 Interface
Serial Port Programming Interface
Communication with the ispPAC81 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the
ispPAC81 as a serial programming interface, and not for boundary scan test purposes. There are no boundary
scan logic cells in the ispPAC81 architecture. This does not prevent the ispPAC81 from functioning correctly, how-
ever, when placed in a valid serial chain with other IEEE 1149.1 compliant devices.
A brief description of the ispPAC81 serial interface follows. For complete details of the reference specification, refer
to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now
includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispPAC81. The TAP controller is a state machine driven with mode and clock inputs. Under the correct protocol,
instructions are shifted into an instruction register which then determines subsequent data input, data output, and
related operations. Device programming is performed by addressing the user register, shifting data in, and then
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executing a program user instruction, after which the data is transferred to internal E
CMOS cells. It is these non-
volatile cells that determine the configuration of the ispPAC81. By cycling the TAP controller through the necessary
states, data can also be shifted out of the user register to verify the current ispPAC81 configuration. Instructions
exist to access all data registers and perform internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification.
Others are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data reg-
isters defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. For
ispPAC81, the bypass register is a one-bit shift register that provides a short path through the device when bound-
ary testing or other operations are not being performed. The ispPAC81, as mentioned, has no boundary scan logic
and therefore no boundary scan register. All instructions relating to boundary scan operations place the ispPAC81
in the BYPASS mode to maintain compliance with the specification. The optional identification register described in
IEEE 1149.1 is also included in the ispPAC81. One additional data register included in the TAP of the ispPAC81 is
the Lattice defined user register. Figure 5 shows how the instruction and various data registers are placed in an
ispPAC81.
Figure 5. ispPAC81 TAP Registers
USER REGISTER
ID REGISTER
BYPASS REGISTER
INSTRUCTION REGISTER
TEST ACCESS PORT
OUTPUT
(TAP) LOGIC
LATCH
TDI
TCK
TMS
TDO
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