isppac81 Lattice Semiconductor Corp., isppac81 Datasheet - Page 14

• Manufacturer Part Number: isppac81
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
In-System Programmability
In-System Programming
The ispPAC81 is an in-system programmable device. This is accomplished by integrating all high voltage program-
ming circuitry on-chip. Programming is performed through a 5-wire, IEEE 1149.1 compliant serial port interface at
normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in non-volatile
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this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E
be configured by the user to store unique data such as ID codes, revision numbers or inventory control data.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispPAC81 device to prevent unauthorized readout of the
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device. This cell can only be erased by reprogramming the device, so the original configuration can not be exam-
ined once programmed. Usage of this feature is optional.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file is created using the PAC-Designer software.
Devices can then be ordered through the usual supply channels with the user’s specific configuration already pre-
loaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production pro-
gramming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Included in the basic ispPAC81 Design Kit is an engineering prototype board that can be connected to the parallel
port of a PC. It demonstrates proper layout techniques for the ispPAC81 and can be used in real time to check cir-
cuit operation as part of the design process. Input and output connections as well as a “breadboard” circuit area
are provided to speed debugging of the circuit.
Figure 4. Configuring the ispPAC81 “In-System” from a PC Parallel Port
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2
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface are described in the interface section of
CMOS user bit patterns. Once programmed, this cell prevents further access to the functional user bits in the
PAC-Designer
Software
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ispDownload
2
Cable (6')
memory of the ispPAC81. It contains 21 bits that can
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ispPAC81
Circuitry
System
Device
Other
ispPAC81 Data Sheet