isppac81 Lattice Semiconductor Corp., isppac81 Datasheet - Page 18

• Manufacturer Part Number: isppac81
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 7. Identification Code (IDCODE) 32-Bit Binary Word for Lattice ispPAC81
ADDUSR (Address User Register) instruction is a Lattice-defined instruction that selects the user register to be
shifted during a Shift-DR operation. Normal operation of a device is not interrupted by this instruction. It precedes a
PRGA or PRGB (Program User A or B) instruction to shift in a new configuration from the user register into either
the A or B configuration memory, and follows a VERA or VERB (Verify User A or B) instruction to shift out the cur-
rent configuration of either A or B configuration memory into the user register. The bit code for this instruction is
shown in Table 5.
The PRGA and PRGB (Program User A or B) are Lattice instructions that enable the data shifted into the user reg-
ister to be programmed into the non-volatile E
its two user configurations. The user register is a 96-bit shift register that contains all the user-controlled parametric
data pertaining to the configuration of the ispPAC81. NOTE: Although the user register length is 96 bits, only the “A”
configuration is that long. The device gain setting bits, UES bits, and security fuse bit are all part of the “A” configu-
ration memory and are not stored at all in “B” memory, which only contains the unique capacitor settings of that
configuration. When initially programming or reprogramming the ispPAC81 with software other than PAC-Designer,
or an authorized third-party programmer (e.g., via microcontroller, refer to the Lattice application note covering the
required algorithms necessary for complete JTAG device programming control of the ispPAC81, specific bit assign-
ments, word lengths, etc.). Normal operation of the device is interrupted during the actual programming time. A
programming operation does not begin until entry of the Run-Test/Idle state. The time required to insure data reten-
tion is given in the TAP signal specifications table. The user must ensure that the recommended programming
times are observed. The bit code for these instructions is shown in Table 5.
VERA and VERB (Verify User A or B) are the next Lattice instructions and cause the current A or B configurations
of the ispPAC81 to be loaded into the user register. This operation doesn’t interrupt operation of the device. The
current configuration of either the A or B configuration memory can then be shifted out of the user register immedi-
ately after an ADDUSR instruction is executed. NOTE: The verification of memory configuration “A” is possible only
when the A/B bit is set to a logic 0. This must be taken into account if verify will be performed at a later time on
parts with unknown configurations (refer to the Lattice application note covering the required algorithms necessary
for complete JTAG device programming control of the ispPAC81, specific bit assignments, word lengths, etc.). If the
A/B bit has been set to a logic 1, it will not be possible to do a VERA command properly. The bit code for this
instruction is shown in Table 5.
ENCAL (Enable Calibration) is a Lattice instruction that enables the start of an auto-calibration sequence. This
operation causes all outputs of the device to go to 2.5V until the calibration sequence is completed (see Timing
Specifications). As with the programming instructions above, calibration does not begin until entry of the Run-Test/
Idle state. The completion of the calibration is not dependent, however, on any further TAP control. This means the
state of the TAP can be returned immediately to the Test-Logic-Reset state. The only consideration would be to not
clock the TAP during critical analog operations. The first several milliseconds of the calibration routine are con-
sumed waiting for configurations to settle, though, leaving more than enough time to clock the TAP back to the Test-
Logic-Reset state. The bit code for this instruction is shown in Table 5.
The last Lattice instructions are ABE and BBE (User A or B Bulk Erase). Operation of the device is interrupted dur-
ing an ABE or BBE, during which all inputs are disconnected and all outputs driven to VREF
mize internal circuitry, programming can only be selectively done in one direction (from zeroes to ones). The ABE
MSB
E
XXXX / 0000 0001 0010 0001 / 0000 0100 001 / 1
2
Version
Configured
(4 bits)
0121h = PAC81
2
Part Number
CMOS memory of the ispPAC81 and thereby alter either or both of
(16 bits)
18
Lattice Semiconductor
JEDEC Manfacturer
Identity Code for
(11 bits)
per 1149.1-1990
Constant 1
(1 bit)
LSB
ispPAC81 Data Sheet
OUT
(2.5V). To econo-