isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 10

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset and feedback
signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener-
ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are
deskewed either at the board level or the device level.
The ispMACH 5000VG devices provide two PLL circuits. PLL0 receives its clock inputs from GCLK 0 and provides
outputs to CLK 0 (CLK 1 when using the secondary clock). PLL1 operates with signals from GCLK 3 and CLK 3
(CLK 2 when using the secondary clock). The PLL outputs (CLK_OUT) are routed via a dedicated net to a dedi-
cated pad. Further the buffers at these dedicated pads are regular I/O buffers that can select either the I/O macro-
cell or the CLK_OUT (CLK_OUT0/CLK_OUT1) signal. The CLK_OUT nets are not routed through the GRP.
Additionally, there are two sets of signals used for external control. Each PLL has a set of PLL_RST, PLL_FBK and
PLL_LOCK signals. Figure 10 shows the ispMACH 5000VG PLL block diagram.
Figure 10. PLL Block Diagram
In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N
and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The
K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and
feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-
ing a stable, high frequency output from the PLL’s VCO circuit.
The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and
clock-to-out times for better performance. This operates by inserting delay on the input or feedback lines in 0.5ns
increments from 0 to 3.5ns. For more information on the PLL, please refer to Technical Note TN1003: ispMACH
5000VG PLL Usage Guidelines .
Power Management
The ispMACH 5000VG devices provide unique power management controls. The devices have two power settings,
high power and low power, on a per node basis. Low power consumption is approximately 50% of high power con-
sumption with a timing delay adder (tLP) to the routing delay of the low power node. Each node can be configured
as either high power or low power. However, care should be taken when sharing product terms between nodes with
different power settings.
The ispMACH 5000VG devices also have a power-off feature for unused product terms. By default, any product
term that is not used is configured as such. This allows the device to operate at minimal power consumption with-
out affecting the timing of the design. For more information on power management, please refer to Technical Note
TN1002: Power Estimation in ispMACH 5000VG Devices .
PLL_FBK
PLL_RST
CLK_IN
Input Clock
(M) Divider
Programable
(N) Divider
Feedback
Delay
Loop
Detector
Phase
VCO
10
and
ispMACH 5000VG Family Data Sheet
Post-scalar
(V) Divider
Secondary
(K) Divider
Clock
PLL_LOCK
SEC_OUT
CLK_OUT
Clock Net
Clock Net