isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 4

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 3. Macrocell Slice
Figure 4. AND-Array
ing with PT0. There is one product term cluster for every macrocell in the GLB. In addition to the three control prod-
uct terms, the first, third, fourth and fifth product terms of each cluster can be used as a PTOE (output macrocells
only), PT Clock, PT Preset and PT Reset, respectively. Figure 4 is a graphical representation of the AND-Array.
68
From
SRP
AND Array
Speed/
Power
Dual-OR Array
In[66]
In[67]
In[0]
Note:
Indicates programmable fuse.
From
n+7
n-7
To
Shared PT Reset
PTSA Bypass
Shared PT Clock
Global Reset
PT Preset
PT Clock
PT Reset
PTSA
BCLK0
BCLK1
BCLK2
BCLK3
4
ispMACH 5000VG Family Data Sheet
PT0
PT1
PT2
PT3
PT4
PT155
PT156
PT157
PT158
PT159
PT162
PT160
PT161
Cluster 0
Shared OE
Macrocell
D
Clk En
Clk
P
Cluster 31
Shared clock
Shared reset
R/L
R
Q
PT OE to
I/O Block
From
I/O Cell
Output
to I/O Block
GRP and SRP