isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 2

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 1. Functional Block Diagram
Overview
The ispMACH 5000VG devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks
(GLBs) interconnected by a tiered routing system. Figure 1 shows the functional block diagram of the ispMACH
5000VG. Groups of four GLBs, referred to as segments, are interconnected via a Segment Routing Pool (SRP).
Segments are interconnected via the Global Routing Pool (GRP.) Together the GLBs and the routing pools allow
designers to create large designs in a single device without compromising performance.
Each GLB has 68 inputs coming from the SRP and contains 163 product terms. These product terms form groups
of five product term clusters, which feed the PT sharing array or the macrocell directly. The ispMACH 5000VG
allows up to 160 product terms to be connected to a single macrocell via the product term expanders and PT Shar-
ing Array.
The macrocell is designed to provide flexible clocking and control functionality with the capability to select between
global, product term and block-level resources. The outputs of the macrocells are fed back into the switch matrices
and, if required, the sysIO cell.
All I/Os in the ispMACH 5000VG family are sysIOs, which are split into four banks. Each bank has a separate I/O
power supply and reference voltage. The sysIO cells allow operation with a wide range of today’s emerging inter-
face standards. Within a bank, inputs can be set to a variety of standards, providing the reference voltage require-
ments of the chosen standards are compatible. Within a bank, the outputs can be set to differing standards,
providing the I/O power supply voltage and the reference voltage requirements of the chosen standard are compat-
ible. Support for this wide range of standards allows designers to achieve significantly higher board-level perfor-
mance compared to the more traditional LVCMOS standards.
GNDP0
GCLK0
GCLK1
V
V
V
V
V
CCO0
CCO1
CCP0
REF0
REF1
PLL0
GLB
GLB
GLB
GLB
GLB
GLB
GLB
GLB
I/O Bank 0
I/O Bank 1
SRP
SRP
SRP
SRP
GLB
GLB
GLB
GLB
GLB
GLB
GLB
GLB
Global Routing Pool
2
GLB
GLB
GLB
GLB
GLB
GLB
GLB
GLB
ispMACH 5000VG Family Data Sheet
I/O Bank 3
I/O Bank 2
SRP
SRP
SRP
SRP
GLB
GLB
GLB
GLB
GLB
GLB
GLB
GLB
PLL1
V
V
GCLK3
V
GNDP1
GCLK2
V
V
CCO3
REF3
CCP1
REF2
CCO2