isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 21

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isppac10

Manufacturer Part Number
isppac10
Description
In-system Programmable Analog Circuit
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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Lattice Semiconductor
ispMACH 51024VG Internal Timing Parameters (Continued)
t
t
t
t
t
t
t
t
t
Control Delays
t
t
t
t
t
t
Notes:
1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
2. t
CES
CEH
SL
SL_PT
HL
GOi
PDLi
SRi
SRR
BCLK
PTCLK
BSR
PTSR
SPTOE
PTOE
Parameter
direction in units of 0.5ns for each step.
PLL_DELAY
is the unit increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to 3.5ns in either
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time
Latch Setup Time with PT Clock
Latch Hold Time
Latch Gate to Output/Feedback MUX Time
Propagation Delay through Transparent Latch to
Output/Feedback MUX
Asynchronous Reset or Set to Output/Feedback
MUX Delay
Asynchronous Reset or Set Recovery Delay
GLB PT Clock Delay
Macrocell PT Clock Delay
Block PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Segment PT OE Delay
Macrocell PT OE Delay
Description
Over Recommended Operating Conditions
21
2.60
0.60
2.80
2.80
0.00
Min Max Min Max Min Max Min Max
-5
ispMACH 5000VG Family Data Sheet
1.75
2.40
0.75
1.00
3.10
3.00
2.00
2.00
2.40
1.40
3.90
0.90
4.20
4.20
0.00
-75
2.50
3.50
1.00
1.50
4.65
4.50
3.00
3.00
3.60
2.10
5.05
1.20
5.50
5.50
0.00
-10
3.50
4.00
1.25
2.00
6.00
6.00
4.00
4.00
7.75
1.75
5.95
1.45
6.60
6.60
0.00
-12
4.50
4.50
1.50
2.50
7.00
7.00
4.80
4.80
9.10
2.10
Timing v.1.10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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