isppac10 Lattice Semiconductor Corp., isppac10 Datasheet - Page 5

• Manufacturer Part Number: isppac10
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Enhanced Dual-OR Array
To facilitate logic functions requiring a very large number of product terms, the ispMACH 5000VG architecture has
been enhanced with an innovative product term expander capability. This capability is embedded in the Dual-OR
Array. The Dual-OR Array consists of 64 OR gates. There are two OR gates per macrocell in the GLB. These OR
gates are referred to as the Expandable PTSA OR gate and the PTSA-Bypass OR gate.
The PTSA-Bypass OR gate receives its five inputs from the combination of product terms associated with the prod-
uct term cluster. The PTSA-Bypass OR gate feeds the macrocell directly for fast narrow logic. The Expandable
PTSA OR gate receives five inputs from the combination of product terms associated with the product term cluster.
It also receives an additional input from the Expanded PTSA OR gate of the N-7 macrocell, where N is the number
of the macrocell associated with the current OR gate. The Expandable PTSA OR gate feeds the PTSA for sharing
with other product terms and the N+7 Expandable PTSA OR gate. This allows cascading of multiple OR gates for
wide functions. There is a small timing adder for each level of expansion. Figure 5 is a graphical representation of
the Enhanced Dual-OR Array.
Figure 5. Enhanced Dual-OR Array
From PT0
From PT1
From PT2
From PT3
From PT4
n
From
n+7
n-7
5
To
ispMACH 5000VG Family Data Sheet
PTSA Bypass
PT Preset
PT Reset
PT Clock
PT OE
To I/O Block
To Macrocell
To PTSA
To Macrocell
To Macrocell
To Macrocell