clc2000 Cadeka Microcircuits LLC., clc2000 Datasheet - Page 14

• Manufacturer Part Number: clc2000
• Description: High Output Current Dual Amplifer
• Manufacturer: Cadeka Microcircuits LLC.

Data Sheet
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, P
P
Quiescent power can be derived from the specified I
ues along with known supply voltage, V
can be calculated as above with the desired signal ampli-
tudes using:
(V
( I
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
Assuming the load is referenced in the middle of the pow-
er rails or V
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the 8 Lead
SOIC packages.
Better thermal ratings can be achieved by maximizing
PC board metallization at the package pins. However, be
careful of stray capacitance on the input pins.
In addition, increased airflow across the package can also
help to reduce the effective Ө
©2004-2008 CADEKA Microcircuits LLC
D
DYNAMIC
LOAD
LOAD
= P
2.5
1.5
0.5
2
1
0
-40
Quiescent
)
)
D
RMS
RMS
can be found from
= (V
Figure 3. Maximum Power Derating
supply
= V
= (V
-20
S+
+ P
PEAK
LOAD
/2.
- V
SOIC-8
Dynamic
LOAD
/ √2
Ambient Temperature (°C)
0
)
RMS
)
RMS
- P
/ Rload
20
Load
× (I
JA
of the package.
eff
LOAD
40
)
RMS
Supply
60
. Load power
80
S
val-
In the event of a short circuit condition, the CLC2000 has
circuitry to limit output drive capability to ±1000mA. This
will only protect against a momentary event. Extended
duration under these conditions will cause junction tem-
peratures to exceed 150°C. Due to internal metallization
constraints, continuous output current should be limited
to ±100mA.
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
R
stability and settling performance. Refer to Figure 4.
Table 1 provides the recommended R
tive loads. The recommended R
peaking in the frequency response. The Frequency Re-
sponse vs. C
the CLC2000.
For a given load capacitance, adjust R
tradeoff between settling time and bandwidth. In general,
reducing R
ditional overshoot and ringing.
S
Input
, between the amplifier and the load to help improve
C
1000
L
100
500
10
20
50
(pF)
R
g
S
Figure 4. Addition of R
+
-
Table 1: Recommended R
will increase bandwidth at the expense of ad-
L
plots, on page 7, illustrates the response of
R
f
R
Capacitive Loads
24.5
13.5
S
40
20
6
5
(Ω)
R
s
C
L
S
-3dB BW (MHz)
S
values result in <=1dB
for Driving
R
S
L
S
275
250
175
135
for various capaci-
75
45
vs. C
S
www.cadeka.com
Output
to optimize the
L
14