hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 3

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

Pin Description
COFSYNC
SOFSYNC
SMBLCLK
THRESH
AOUT9-0
BOUT9-0
SLOCLK
SERCLK
SSYNC
QIN9-0
FZ_ST
FZ_CT
NAME
SYNC
LKINT
QSER
IIN9-0
HI/LO
ISER
GND
C7-0
COF
SOF
A2-0
OEA
OEB
V
CLK
WR
RD
CC
TYPE
I/O
O
O
O
O
O
O
O
O
O
O
0
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Quadrature Parallel Input. Data may be two’s complement or offset binary format (see Table 14). These inputs are
+5V Power Supply.
Ground.
In-Phase Parallel Input. Data may be two’s complement or offset binary format (see Table 14). These inputs are
sampled by CLK when the SYNC signal is active Low. IIN9 is the MSB. See Input Controller Section.
sampled by CLK when the SYNC signal is active Low. QIN9 is the MSB. See Input Controller Section.
Data Sync. When SYNC is asserted “Low”, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the
rising edge of CLK.
Carrier Offset Frequency. The frequency term generated by the Carrier Tracking Loop Filter is output serially via this
pin. The new offset frequency is shifted out MSB first by CLK or SLOCLK starting with the clock cycle after the
assertion of COFSYNC.
Carrier Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data
word. (Programmable Polarity, see Table 41, bit 11).
Sampler Offset Frequency. Sample frequency correction term generated by the Symbol Tracking Loop Filter is output
serially via this pin. The frequency word is shifted out MSB first by CLK or SLOCLK starting with the clock cycle after
assertion of SOFSYNC.
Sampler Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial
data word. (Programmable Polarity, see Table 41, bit 12).
Address Bus. The address on these pins specify a target register for reading or writing (see Microprocessor Interface
Section). A0 is the LSB.
Microprocessor Interface Data Bus. This bi-directional bus is used for reading and writing to the processor interface.
These are the data I/O pins for the processor interface. C0 is the LSB.
Write. This is the write strobe for the processor interface (see Microprocessor Interface Section).
Read. This is the read enable for the processor interface (see Microprocessor Interface Section).
Freeze Symbol Tracking Loop. Asserting this pin “high” zeroes the sampling error into the Symbol Tracking Loop
Filter (see Symbol Tracking Loop Filter Section).
Freeze Carrier Tracking Loop. Asserting this pin “high” zeroes the carrier Phase Error input to the Carrier Tracking
Loop Filter.
Lock Detect Interrupt. This pin is asserted “high” for at least 4 CLK cycles when the Lock Detector Integration cycle
is finished (see Lock Detector Section). Used as an interrupt for a processor. The Lock Detect Interrupt may be
asserted “high” longer than 4 CLK cycles, depending on the Lock Detector mode.
Threshold Exceeded. This output is asserted “low” when the magnitude out of the Cartesian to Polar converter
exceeds the programmable Power Detect Threshold (see Table 15 and AGC Section).
Slow Clock. Optional serial clock used for outputting data from the Carrier and Symbol Tracking Loop Filters. The
clock is programmable and has a 50% duty cycle. Note: Not used when the HSP50110 is used with the
HSP50210 (see Table 41).
In-Phase Serial Input. Serial data input for In-Phase Data. Data on this pin is shifted in MSB first and is synchronous
to SERCLK (see Input Controller Section).
Quadrature Serial Input. Serial data input for Quadrature Data. Data on this pin is shifted in MSB first and is
synchronous to SERCLK (see Input Controller Section).
Serial Word Sync. This input is asserted “high” one CLK before the first data bit of the serial word (see Figure 2).
Serial Clock. May be asynchronous to other clocks. Used to clock in serial data (see Input Controller Section).
A Output. Data on this output depend on the configuration of Output Selector. AOUT9 is the MSB (see Table 42).
B Output. Data on this output depend on the configuration of Output Selector. BOUT9 is the MSB (see Table 42).
Symbol Clock. 50% duty cycle clock aligned with soft bit decisions (see Figure 19).
A Output Enable. This pin is the three-state control pin for the AOUT9-0. When OEA is high, the AOUT9-0 is high
impedance.
B Output Enable. This pin is the three-state control pin for the BOUT9-0. When OEB is high, the AOUT9-0 is high
impedance.
HI/LO. The output of the Input Level Detector is provided on this pin (see Input Level Detector Section). This signal
can be externally averaged and used to control the gain of an amplifier to close an AGC loop around the A/D
converter. This type of AGC sets the level based on the median value on the input.
System Clock. Asynchronous to the processor interface and serial inputs.
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HSP50210
DESCRIPTION