hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 42

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hsp50210

Manufacturer Part Number
hsp50210
Description
Digital Costas Loop
Manufacturer
Intersil Corporation
Datasheet

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POSITION
BIT
9-8
6-4
2-0
10
7
3
Serial Clock Phase
Relative to Data
Serial Clock Divider
Serial Clock Select for
COF Output
Serial Word Length for
COF Output
Serial Clock Select for
SOF Output
Serial Word Length for
SOF Output
FUNCTION
TABLE 41. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER (Continued)
3-42
0 = Rising edge of serial clock at center of data bit.
1 = Falling edge of serial clock at center of data bit. Set to 0 for use with the HSP50110.
These bits set the clock rate of SLOCLK.
00 -> SLOCLK = CLK/2.
01 -> SLOCLK = CLK/4.
10 -> SLOCLK = CLK/8.
11 -> SLOCLK = CLK/16.
0 = CLK is used as the serial clock.
1 = SLOCLK is used as the serial clock.
Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial
clock for the SOF and COF outputs, and the same CLK must be used by both chips.
000 = 8 Bits
001 = 12 Bits
010 = 16 Bits
011 = 20 Bits
100 = 24 Bits
101 = 28 Bits
110 = 32 Bits
111 = 40 Bits
0 = CLK is used as the serial clock.
1 = SLOCLK is used as the serial clock.
Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial
clock for the SOF and COF outputs, and the same CLK must be used by both chips.
000 = 8 Bits
001 = 12 Bits
010 = 16 Bits
011 = 20 Bits
100 = 24 Bits
101 = 28 Bits
110 = 32 Bits
111 = 40 Bits
DESTINATION ADDRESS = 27
HSP50210
DESCRIPTION

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