ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 38

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
present only during reset. If mcs0_n has been programmed as the chip select for the whole
middle chip select address range, these pins may be used as PIOs.
2.2.25 mcs3_n/rfsh_n/pio25—Midrange Memory Chip Select (synchronous outputs with
The mcs3_n pin provides an indication that a memory access is in progress to the fourth region
of the midrange memory block. The size of the Midrange Memory Block and its base address
are programmable. The mcs3_n may be configured for either an 8- or 16-bit bus width for the
IA186ES microcontroller by the Auxiliary Configuration Register (AUXCON Bit [1]) and is
held high during bus hold. If mcs0_n has been programmed as the chip select for the whole
middle chip select address range, this pin may be used as PIO. Furthermore, this pin has a weak
pullup that is only present during reset.
The rfsh_n signal is timed for auto refresh to PSRAM or DRAM devices. The refresh pulse is
only output when the PSRAM or DRAM mode bit is set (EDRAM register Bit [15]). This pulse
is of 1.5 clock pulse duration with the rest of the refresh cycle made up of a deassertion period
such that the overall refresh time is met. Finally this pin is not tristated during a bus hold.
2.2.26 nmi—Nonmaskable Interrupt (synchronous edge-sensitive input)
This is the highest priority interrupt signal and cannot be masked, unlike int6–int0.
Program execution is transferred to the nonmaskable interrupt vector in the interrupt vector table,
upon the assertion of this interrupt (transition from low to high), and this interrupt is initiated at
the next instruction boundary. For recognition to be assured, the nmi pin must be held high for at
least a clkouta period.
The nmi is not involved in the priority resolution process, which deals with the maskable
interrupts and does not have an associated interrupt flag. This allows for a new nmi request to
interrupt an nmi service routine that is already underway. The interrupt flag IF is cleared,
disabling the maskable interrupts, when an interrupt is taken by the processor. If, during the nmi
service routine, the maskable interrupts are re-enabled, by use of STI instruction for example, the
priority resolution of maskable interrupts will be unaffected by the servicing of the nmi. For this
reason, it is strongly recommended that the nmi interrupt service routine does not enable the
maskable interrupts.
2.2.27 pcs1_n–pcs0_n (pio17–pio16)—Peripheral Chip Selects 1–0 (synchronous
These pins provide an indication that a memory access is under way for the second and first
regions, respectively, of the peripheral memory block (I/O or memory address space). The base
address of the peripheral memory block is programmable. The pcs3_n–pcs0_n are held high
internal pullup)/Automatic Refresh (synchronous output)
outputs)
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IA211050902-15
December 24, 2008
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