ia186xl Innovasic Semiconductor Inc., ia186xl Datasheet - Page 28

• Manufacturer Part Number: ia186xl
• Description: 16-bit Microcontroller
• Manufacturer: Innovasic Semiconductor Inc.

IA186XL/IA188XL
16-Bit Microcontrollers
Table 7. IA186XL Pin/Signal Descriptions (Continued)
rd_n
res_n
reset
s0_n
s1_n
s2_n
s3
s4
s5
s6
srdy
test_n
tmr in 0
Signal
rd_n/qsmd_n
test_n/busy
tmr in 0
a16/s3
a17/s4
a18/s5
a19/s6
Name
res_n
reset
s0_n
s1_n
s2_n
srdy
®
PLCC
62
24
57
52
53
54
68
67
66
65
49
47
20
Pin
UNCONTROLLED WHEN PRINTED OR COPIED
PQFP
55
18
23
22
21
27
29
59
9
3
4
5
6
ENG211080711-01
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LQFP
28
73
34
40
39
38
21
22
23
24
44
46
77
read. output. Active Low. When asserted
(low), rd_n indicates that the accessed
memory or I/O device must drive data from the
location being accessed onto the data bus.
res_n causes the processor to immediately
terminate its present activity, clear the internal
logic, and enter a dormant state.
reset is an output signal indicating the CPU is
being reset and can be used as a system rest.
status [2:0]_n are outputs. During a bus
cycle, the status (i.e., type) of cycle is encoded
on these lines as follows:
s2_n s1_n s0_n
status [6:3] are Inputs/Outputs.
Bus Cycle A19/s6 A18/s5 A17/s4 A16/s3
____________
N = 0 for CPU bus cycle.
N = 1 for DMA or refresh cycle.
synchronous ready
test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA186XL to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
0
0
0
0
1
1
1
1
T
T
T
T
T
w
1
2
3
4
0
0
1
1
0
0
1
1
A19
N
N
N
N
0
1
0
1
0
1
0
1
Description
A18
Bus Cycle Status
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
No Bus Activity
Preliminary Data Sheet
0
0
0
0
September 30, 2008
http://www.Innovasic.com
A17
0
0
0
0
Customer Support:
1-888-824-4184
A16
0
0
0
0