ia186xl Innovasic Semiconductor Inc., ia186xl Datasheet - Page 41

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ia186xl

Manufacturer Part Number
ia186xl
Description
16-bit Microcontroller
Manufacturer
Innovasic Semiconductor Inc.
Datasheet

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IA186XL/IA188XL
Preliminary Data Sheet
16-Bit Microcontrollers
September 30, 2008
Figure 11. Clock Circuit Connection Options
4.1.5 Chip-Select/Ready Generation Logic
The IA186XL provides programmable chip-select generation for both memories and peripherals.
The chip can be programmed to provide READY or WAIT state generation. It can also provide
latched address bits A1 and A2. The select lines are active for all memory and I/O cycles in their
programmed areas whether signals are generated by the CPU or by the DMA unit. The
IA186XL provides six memory chip select outputs for three address areas; upper memory, lower
memory, and midrange memory. One signal is provided for upper memory, one for lower
memory and four for midrange memory (see Figure 12).
The IA186XL provides a chip select, called UCS, for upper memory. Upper memory is usually
used for system memory because the IA186XL begins executing at memory location FFFF0H
after reset. The IA186XL provides a chip select for low memory called LCS. Low memory
contains the interrupt vector table starting at location 00000H. For midrange memory, the
IA186XL provides four MCS lines that are active within a user-locatable memory block. This
block can be located within 1 Mbyte of memory address space exclusive of the areas defined by
UCS and LCS. Both the base address and size of this memory block are programmable.
®
ENG211080711-01
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