ak4682 AKM Semiconductor, Inc., ak4682 Datasheet
ak4682
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ak4682 Summary of contents
Page 1
... Multi-channel CODEC with 2Vrms Stereo Selector The AK4682 is a single chip CODEC that includes two channels of ADC and four channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range ...
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... LIN4 LIN5 LIN6 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 2Vrms LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3 MS0610-E- AK4682 Block Diagram - 2 - [AK4682] PORTB MCLKB 2ch HPF, Serial BICKB LRCKB ADC DVOL I/F SDTOB MSB PORTA MCLKA 2ch DVOL Serial BICKA Stereo ...
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... Pin Layout LIN3 37 RIN3 LIN4 40 RIN4 LIN5 43 RIN5 LIN6 46 RIN6 47 DVDD1 48 MS0610-E-01 -20 ∼ +85°C 48pin LQFP (0.5mm pitch) Evaluation Board AK4682EQ Top View - 3 - [AK4682] 24 LOUT3 23 PVSS 22 PVDD 21 ROUT2 20 LOUT2 19 MSB 18 ROUT1 17 LOUT1 16 DVSS2 15 DVDD2 14 SCL 13 SDA 2007/07 ...
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... Audio Serial Data Output B Pin Power-Down Mode & Reset Pin 7 PDN I When “L”, the AK4682 is powered-down, all registers are reset. And then all digital output pins go “L”. The AK4682 must be reset once upon power-up. 8 LRCKA I Input Channel Clock A Pin ...
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... LOUT1-3, ROUT1-3, LIN1-6, RIN1-6 SDTOB, LRCKB(Master), BICKB(Master) MCLKA, LRCKA, BICKA, SDTIA1-2, MCLKB, Digital LRCKB(Slave), BICKB(Slave), MSB SDA, SCL MS0610-E-01 PIN/FUNCTION (continued) Function Setting These pins should be open. These pins should be open. These pins should be connected to DVSS. These pins should be pulled-up to DVDD2 [AK4682] 2007/07 ...
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... MS0610-E-01 ABSOLUTE MAXIMUM RATINGS Symbol TVDD DVDD1 DVDD2 AVDD1 AVDD2 PVDD IIN VIND1 VIND2 VIND3 VINA1 Ta Tstg Symbol min TVDD 2.7 DVDD1 4.75 DVDD2 4.75 AVDD1 4.75 AVDD2 4.75 PVDD 8 [AK4682] min max Units -0.3 6.0 V -0.3 6.0 V -0.3 6.0 V -0.3 6.0 V -0.3 6.0 V -0.3 14.0 V ± -0.3 DVDD1+0.3 V -0.3 DVDD2+0.3 V -0.3 TVDD+0 ...
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... Units dB dB kΩ Vrms dB Bits ppm/°C Vrms dB Bits ppm/°C Vrms kΩ 2007/07 ...
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... Units μA μA μA μA Units kHz kHz kHz kHz dB dB 1/fs µ kHz kHz kHz 2007/07 ...
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... PDN “↑” to SDTOB valid (Note: 12) Note: 10 MCLKB supports only the normal mode (256fsn, 384fsn, 512fsn, 768fsn). Note: 11 The AK4682 can be reset by bringing the PDN pin = “L”. Note: 12 These cycles are the number of LRCKB rising from PDN rising. MS0610-E-01 ...
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... [AK4682] min typ max Units 324 ns 128 ns 128 ...
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... Clock Timing (Normal mode) 1/fCLK tCLKH tCLKL 1/fsn, 1/fsd tLRH tLRL tBCK tBCKH tBCKL Clock Timing (TDM 128 mode [AK4682] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL LRCK= LRCKB, LRCKA, BICK= BICKA, BICKB, SDTI= SDTIA, SDTO= SDTOB ...
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... LRCK tBLR BICK SDTO SDTI MS0610-E-01 tLRB tLRS tSDS tSDH Audio Interface Timing (Normal mode) tLRB tSDS tSDH Audio Interface Timing (TDM 128 mode [AK4682] VIH VIL VIH VIL tBSD 50% TVDD VIH VIL VIH VIL VIH VIL tBSD 50%TVDD VIH VIL ...
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... Stop Start MS0610-E-01 tMBLR Audio Interface timing (Master Mode) tPD tPDV Power Down & Reset Timing tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start Bus mode Timing - 13 - [AK4682] 50% TVDD 50% TVDD tBSD 50% TVDD VIH VIL 50% TVDD VIH VIL tSP VIH VIL tSU:STO Stop 2007/07 ...
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... The AK4682 is slave mode at power-down (PDN pin = “L”). To change to the master mode, set MSB pin “H” or write “1” to MSB bit. Until when setting MSB pin “H” or writing “1” to MSB bit, LRCKB and BICKB pins are input pins. ...
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... Sampling Speed 512fs 768fs 16.3840 24.5760 Normal 22.5792 33.8688 24.5760 36.8640 (default) 32kHz~48kHz 64kHz~96kHz 120kHz~192kHz - BICKA (MHz) 768fs 64fs 24.5760 2.0480 33.8688 2.8224 36.8640 3.0720 BICKA (MHz) 384fs 64fs 33.8688 5.6448 36.8640 6.1440 [AK4682] 2007/07 ...
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... TDMA bit = “0” TDMA bit = “1” SDTIA1 L1, R1 SDTIA2 L2, R2 Table 11. DAC2 Source Control - 16 - BICKA (MHz) 384fs 64fs - 11.2896 - 12.2880 32kHz~48kHz 64kHz~96kHz 120kHz~192kHz Sampling Speed 512fs 768fs 16.3840 24.5760 Normal 22.5792 33.8688 24.5760 36.8640 - - Double - - - - Quad - - (default) (default) [AK4682] 2007/07 ...
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... TDM 128 mode: TDMA bit = “1” The TDMA bits = “1” set the AK4682 audio serial interface format to the TDM 128 mode. The four channel serial data (SDTIA1 input to the SDTIA1 pin. The data of SDTIA2 pin is not used. The TDM 128 mode is not available in Quad Speed Mode ...
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... 24bit 24bit 24bit 24bit 24bit 24bit 24bit [AK4682] LRCKB BICKB L/R I/O speed I/O ≥ 48fs H ≥ 48fs H ≥ 48fs H ≥ 48fs L (default) H/L O 64fs ...
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... Rch Data Don’t Care Rch Data Don’t Care Rch Data [AK4682 2007/07 ...
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... Figure 6. Mode 9 Timing 128 BIC Figure 7. Mode 10 Timing - [AK4682] 2007/07 ...
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... LRCKA (m ode 11) BICKA(128fs) SDTIA1( on’t C are) SDTIA2(i) MS0610-E-01 128 BIC Figure 8. Mode 11 Timing - [AK4682] 2007/07 ...
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... Digital Volume Control The AK4682 has channel-independent digital volume control (256 levels, 0.5dB step). The IATL7-0, IATR7-0 bits set the volume level of each ADC channel (Table 16). The OAT1L7-0, OAT1R7-0, OAT2L7-0 and OAT2R7-0 bits set each DAC channel (Table 17). ATSAD (ATSDA) bits (Table 18, Table 19) control the transition time of attenuation. The transition between each attenuation level is the soft transition ...
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... The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. MS0610-E-01 (1) GD (2) Figure 9. Soft Mute Function - 23 - [AK4682] (1) (3) GD 2007/07 ...
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... Stereo Matrix Control The AK4682 has independent stereo matrix control for DAC1 and DAC2. The PL23-20 and PL13-10 bits control each matrix. PL13 PL12 PL11 PL10 ...
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... If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. Figure 10. Soft Mute Function for Stereo Matrix Control MS0610-E-01 (L+R)/ (1) (1) (1) GD (2) GD (2) (L+R)/ (3) (3) ( [AK4682] 2007/07 ...
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... Input Selector, Input Attenuator The AK4682 includes 8:4 stereo input/output selectors. The AIN2-0, AOUT12-10, AOUT22-20, AOUT32-30 bits set each input channel (Table 22, Table 23, Table 24, Table 25). To select the DAC1 or DAC2, set PWAD bit = PWDA bit = PWANA bit = “1”. AIN3 bit ...
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... The period of (1) varies in the setting value of DATT. It takes 1028/fs to mute when DATT value is +24dB. When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms because there is some DC difference between the channels. MS0610-E-01 (1) -∞ LIN 1 [AK4682] (1) (2) LIN 2 2007/07 ...
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... Power ON/OFF Sequence The each block of the AK4682 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the DAC outputs go to AVDD2 voltage and SDTOB pin goes to “ ...
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... Digital Block Power-down Init Cycle Digital Block Power-down (2) GD (3) “0”data “0”data (2) GD (6) (5) (6) (7) Don’t care BICKA (BICKB), LRCKA (LRCKB)) can be stopped in the reset mode. Figure 13. Reset sequence example - 29 - [AK4682] Normal Operation Normal Operation GD (4) GD MCLKA (MCLKB), 2007/07 ...
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... All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4682 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE) ...
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... In the read mode, the slave, the AK4682 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data ...
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... The AK4682 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4682 generates an acknowledge, and awaits the next data again. The master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 0DH prior to generating the stop condition, the address counter will “ ...
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... After receipt of the slave address with R/W bit set to “1”, the AK4682 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter the master does ...
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... OAT2R7 OAT2R6 OAT2R5 OAT2R4 OAT2R3 OAT2R2 OAT2R1 OAT2R0 - SMAD SMDA TDMA DIFA1 DAC2 DAC1 ATSAD ATSDA 0 CKSB1 CKSB0 PL13 PL12 PL11 AIN3 AIN2 AIN1 IATL3 IATL2 IATL1 IATR3 IATR2 IATR1 [AK4682] D0 RSTN 0 DIFA0 MSB PL10 AIN0 IATL0 IATR0 2007/07 ...
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... PWANA PWDA PWAD DIFB1 DIFB0 [AK4682 SMAD SMDA RSTN TDMA DIFA1 DIFA0 2007/07 ...
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... ACKS DFS1 DFS0 PL23 PL22 PL21 PL20 [AK4682 DAC2 DAC1 ATSAD ATSDA CKSB1 CKSB0 MSB PL13 PL12 PL11 PL10 ...
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... LIN2/RIN2 0010: LIN3/RIN3 0011: LIN4/RIN4 0100: LIN5/RIN5 0101: LIN6/RIN6 0110: DAC1L/DAC1R 0111: DAC2L/DAC2R 1xxx: Mute (x: don’t care) MS0610-E- [AK4682 AIN3 AIN2 AIN1 AIN0 2007/07 ...
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... OAT1R7 OAT1R6 OAT1R5 OAT1R4 OAT1R3 OAT1R2 OAT1R1 OAT1R0 OAT2L7 OAT2L6 OAT2L5 OAT2L4 OAT2L3 OAT2L2 OAT2L1 OAT2L0 OAT2R7 OAT2R6 OAT2R5 OAT2R4 OAT2R3 OAT2R2 OAT2R1 OAT2R0 IATL3 IATL2 IATL1 IATR3 IATR2 IATR1 [AK4682] D0 IATL0 IATR0 2007/07 ...
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... Analog in + 10u 0.1u 1 DVSS1 MCLKB 2 TVDD 3 0.1u LRCKB 4 5 BICKB 6 SDTOB 7 PDN 8 LRCKA BICKA 9 MCLKA 10 SDTIA1 11 SDTIA2 Digital Analog out - 39 - RIN2 36 LIN2 35 Analog RIN1 33 LIN1 32 0.1u 10u 5V Analog AVDD1 31 + AVSS1 30 VCOM3 29 VCOM36 AVSS2 27 10u + 5V Analog 26 AVDD2 0.1u 25 ROUT3 + 9V to 12V [AK4682] Analog 2007/07 ...
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... The internal digital HPF removes the DC offset. The AK4682 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4682 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...
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... LQFP(Unit: mm 0.5 ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0610-E-01 PACKAGE 9.0 ± 0.2 7 0.22 ± 0.08 0.10 M 0° ∼ 10° 0.5 ± 0.2 0.10 Epoxy Cu Solder (Pb free) plate - 41 - 1.70Max 0.13 ± 0.13 1.40 ± 0.05 0.145 ± 0.05 [AK4682] 2007/07 ...
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... Date (YY/MM/DD) Revision 07/04/24 00 07/07/02 01 MS0610-E-01 MARKING AK4682EQ XXXXXXX 1 1) Pin #1 indication 2) Asahi Kasei Logo 3) Marking Code: AK4682EQ 4) Date Code: XXXXXXX (7 digits) REVISION HISTORY Reason Page Contents First Edition Audio Interface Timing (Normal and TDM128 Error Correct 12 mode) were changed [AK4682] 2007/07 ...
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... AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0610-E-01 IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the Note2 [AK4682] in any safety, life support, Note1) 2007/07 ...