ak4682 AKM Semiconductor, Inc., ak4682 Datasheet - Page 29

• Manufacturer Part Number: ak4682
• Description: Multi-channel Codec With 2vrms Stereo Selector
• Manufacturer: AKM Semiconductor, Inc.

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When RSTN bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The DAC outputs
go to AVDD2 voltage and SDTOB pins go to “L”. Because some click noise occurs, the analog output should muted
externally if the click noise influences system application. The Figure 13 shows the power-up sequence.
Notes:
MS0610-E-01
Reset Function
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
(5) When RSTN bit = “0”, the analog outputs go to AVDD2 voltage.
(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”. This
(7) The external clocks (
(8) There is a delay about 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
delay (GD).
noise influences system application.
noise is output even if “0” data is input.
When exiting the reset mode, “1” should be written to RSTN bit after the external clocks (
BICKA (BICKB), LRCKA (LRCKB)) are fed.
DAC Internal
DAC In
Clock In
MCLK,LRCK,SCLK
DAC Out
ADC Internal
ADC In
ADC Out
RSTN bit
Internal
RSTN bit
(Digital)
(Analog)
(Analog)
(Digital)
State
State
MCLKA (MCLKB),
Normal Operation
Normal Operation
GD
Figure 13. Reset sequence example
GD
(2)
(2)
BICKA (BICKB), LRCKA (LRCKB)) can be stopped in the reset mode.
Digital Block Power-down
Digital Block Power-down
(6)
(7)
4~5/fs (8)
Don’t care
“0”data
“0”data
(5)
- 29 -
(3)
(6)
1~2/fs (8)
Init Cycle
516/fs
(1)
Normal Operation
(4)
Normal Operation
GD
GD
MCLKA (MCLKB),
[AK4682]
2007/07