ml7074-001ga Oki Semiconductor, ml7074-001ga Datasheet - Page 21

• Manufacturer Part Number: ml7074-001ga
• Description: Speech Codec
• Manufacturer: Oki Semiconductor

This is the output pin for the analog signal ground potential. The output potential at this pin will be about 1.4 V.
These are the pins for either connecting the crystal oscillator for the master clock or for inputting an external
The operation of the master clock oscillator will be stopped during a power-down due to the PDNB signal, or
This is the power-down control input pin. Power-down mode is entered when this pin goes to “0”. In addition,
Further, it is possible to carry out a power-down reset of the ML7074 when the power is being supplied, by
The READY signal (CR5-B7) goes to “1” about 1.0 second after the power-down mode is released thereby
Notice: At the time of switching on the power, start from the power-down mode using PDNB.
These are power supply pins. DV
AVREF
Connect a 2.2 to 4.7 µF (aluminum electrolytic type) capacitor and a 0.1 µF (ceramic type) capacitor in parallel
between this pin and the GND pin as bypass capacitors. The output at the AVREF pin goes to 0.0 V in the
power-down mode. The voltage starts rising after the power-down mode is released (PDNB = “1” and also CR0-
B7 = “0”). The rise time is about 0.6 sec.
XI, XO
master clock signal.
during a software power-down due to CR0-B7 (SPDN). The oscillator operation starts when the power-down
condition is released, and the ML7074’s internal clock will be started after counting up the oscillation
stabilization period (of about 16 ms). Examples of crystal oscillator connection and external master clock input
are shown in figure 10.
PDNB
this pin also has the function of resetting the ML7074. In order to prevent wrong operation of the ML7074, carry
out the initial power-down reset after switching on the power using this PDNB pin. Also, keep the PDNB pin at
“0” level for 1 µs or more to initiate the power-down state.
performing control of CR0-B7 (SPDN) in the sequence “0” → “1” → “0”.
entering the mode in which various functions are set (initialization mode). See figure 1 for the timing of PDNB
and AVREF, XO, and the initialization mode.
DV
power supply pin for the analog circuits of the ML7074. Connect DGND and AGND together near the ML7074
with a 10 µF electrolytic capacitor and a 0.1 µF ceramic capacitor, as bypass capacitors, in parallel between these
pins. See figure 12 circuit diagram.
Oki Semiconductor
DD
0, DV
CR0-B7
(SPDN)
PDNB
DD
1, DV
C1
XI
DD
2, AV
Figure 10 Examples of oscillator circuit and clock input
X’tal
DD
R
C2
DD
0, 1, 2 are the power supply pins for the digital circuits while AV
XO
To internal
circuits
CR0-B7
(SPDN)
PDNB
XI
Daishinku Co., Ltd.
X’tal(4.096 MHz)
4.096 MHz
AT-49
Open
XO
To internal
circuits
5pF
C1
ML7074-001GA
10pF
C2
1MΩ
DD
R
is the
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