ml7074-001ga Oki Semiconductor, ml7074-001ga Datasheet - Page 23

• Manufacturer Part Number: ml7074-001ga
• Description: Speech Codec
• Manufacturer: Oki Semiconductor

• FR0B (In frame mode, CR11-B7 = “0”)
• DMARQ0B (In DMA mode, CR11-B7 = “1”)
• DMARQ1B (In DMA mode, CR11-B7 = “1”)
These are the address input pins for use during an access of the frame, DMA, or control registers. The addresses
Transmit buffer (TX Buffer)
A7 to A0 = 10xxxxxxb (the lower 6 bits are not valid)
Receive buffer (RX Buffer)
A7 to A0 = 01xxxxxxb (the lower 6 bits are not valid)
Control register (CR)
A7 to A0 = 00xxxxxxb
These are the data input/output pins for use during an access of the frame, DMA, or control registers. Connect
This is the chip select input pin for use during a frame or control register access.
This is the read enable input pin for use during a frame, DMA, or control register access.
This is the write enable input pin for use during a frame, DMA, or control register access.
• FR1B (In frame mode, CR11-B7 = “0”)
A0 to A7
are shown below:
D0 to D15
pull-up resistors to these pins since they are I/O pins. When the 8-bit bus access method is selected by CR11-B5,
only D0 to D7 become valid. Since the higher 8 bits D8 to D15 will always be in the input state when the 8-bit
bus access method is selected (CR11-B5 = “1”), tie them to “0” or “1” inputs.
CSB
RDB
WRB
FR0B (DMARQ0B)
FR1B (DMARQ1B)
Oki Semiconductor
This is the transmit frame output pin which outputs the signal when the transmit buffer is full during frame
access. This pin outputs an “L” level when the transmit buffer becomes full, and maintains that “L” level
output until a specific number of words are read out from the ML7074.
This is the DMA request output pin which outputs the signal when the transmit buffer is full during DMA
access. This output becomes “L” when the transmit buffer becomes full, and returns to the “H” level
automatically on the falling edge of the read enable signal (RDB = “1” → “0”) when there is an
acknowledgement signal (ACK0B = “0”) from the ML7074. This relationship is repeated until a specific
number of words are read out from the ML7074.
This is the receive frame output pin which outputs the signal when the receive buffer is empty during frame
access. This pin outputs an “L” level when the receive buffer becomes empty, and maintains that “L” level
output until a specific number of words are written from the ML7074.
This is the DMA request output pin which outputs the signal when the receive buffer is empty during DMA
access. This output becomes “L” when the receive buffer becomes empty, and returns to the “H” level
automatically on the falling edge of the write enable signal (WRB = “1” → “0”) when there is an
acknowledgement signal (ACK1B = “0”) from the ML7074. This relationship is repeated until a specific
number of words are written from the ML7074.
ML7074-001GA
19