ml7074-001ga Oki Semiconductor, ml7074-001ga Datasheet - Page 24

• Manufacturer Part Number: ml7074-001ga
• Description: Speech Codec
• Manufacturer: Oki Semiconductor

Note: The input/output control and frequencies of the above SYNC and BLCK signals will be as shown in Table
This is the DMA acknowledgement input pin for the DMARQ0B signal during DMA access of the transmit
Tie this pin to “1” when using this ML7074 in the frame access mode (CR11-B7 = “0”).
This is the DMA acknowledgement input pin for the DMARQ1B signal during DMA access of the receive buffer
Tie this pin to “1” when using this ML7074 in the frame access mode (CR11-B7 = “0”).
These are general-purpose input pins. The state (“1” or “0”) of each of these GPI0 and GPI1 pins can be read out
These are general-purpose output pins. The values set in CR17-B0 and CR17-B1 are output at these pins GPO0
This is the input/output control input pin of SYNC and BCLK. The pin becomes input at “0” level and output at
This is the 8 kHz sync signal input/output pin of PCM signals. When CLKSEL is “0”, input continuously an 8
This is the shift clock input/output pin for the PCM signal. When CLKSEL is “0”, it is necessary to input to this
ACK0B
buffer and becomes valid in the DMA mode (CR11-B7 = “1”).
ACK1B
and becomes valid in the DMA mode (CR11-B7 = “1”).
GPI0, GPI1
respectively from CR16-B0 and CR16-B1. Further, GPI0 becomes the input pin for the dial pulse detector
(DPDET) in the secondary functions.
GPO0, GPO1
and GPO1, respectively. Further, GPO0 becomes the output pin for the dial pulse generator (DPGEN) in the
secondary functions.
CLKSEL
“1” level.
SYNC
kHz clock synchronous with BCLK. Further, when CLKSEL is “1”, this pin outputs an 8 kHz clock
synchronous with BCLK. Long frame synchronization is used when CR0-B1 (LONG/SHORT) is “0” and short
frame synchronization is used when it is “1”.
BCLK
pin a clock signal that is synchronous with SYNC. Input a 64 to 2048 kHz clock when the G.711 mode or the
G.726 mode has been selected, and input a 128 to 2048 kHz clock when the 16-bit linear mode has been selected.
When CLKSEL is “1”, this pin outputs a clock that is synchronous with SYNC. This pin outputs a 64 kHz clock
when the G.711 mode or the G.726 mode has been selected, and outputs an 128 kHz clock when the 16-bit linear
mode or G.729.A mode has been selected.
Table 1 Input/output control of SYNC and BCLK
Oki Semiconductor
CLKSEL
“0”
“1”
1 below.
(8 kHz)
(8 kHz)
Output
SYNC
Input
(64 kHz to 2048 kHz)
(64 kHz or 128 kHz)
Output
BCLK
Input
Input a continuous clock after starting the power supply.
Input a 64 to 2048 kHz clock when G.711 or G.726 is selected.
Input a 128 to 2048 kHz clock when 16-bit linear mode is
selected.
An “L” level is output during the power-down mode.
A 64 kHz clock is output when G.711 or G.726 is selected.
A 128 kHz clock is output when G.729.A or 16-bit linear mode
is selected.
Remarks
ML7074-001GA
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