ml87v5002 Oki Semiconductor, ml87v5002 Datasheet - Page 28

• Manufacturer Part Number: ml87v5002
• Description: Audio Delay Ic With Built-in 2-mbit Dram
• Manufacturer: Oki Semiconductor

Register Name
OKI Semiconductor
Default Value
Operation Status
DATA_BIT
Register Name
WR
DRAM_RDY
RD
SRC_CHG
SRC_CLK
CFG_ERS
RUN
INIT
Table 31 Descriptions of Operation Status Register Functions
RUN
BIT7
V
0
* When various settings are correct after the ENBL bit is set to ‘1’ and input data formats
* This bit is changed to ‘1’ when the input masking is performed by changing of input and
* This bit is changed to ‘0’ when the clock masking is performed by changing of input
1: Indicates any inconsistency arises from the various setting values.
0: ---
* The delay operation is not started when the ENBL bit is set while this bit is being set.
1: Indicates the initialization of the internal DRAM is completed and normal operations
0: Indicates the internal DRAM is being initialized.
* When the ENBL bit is set while this bit is being set, the delay operation is postponed
SUB_ADDRESS=08h(R/W)
1: Indicates that the delay operation is being performed.
0: Indicates that the delay operation is being suspended.
1: Indicates the input switching sequence is ready when switching 8ch
0: ---
1: Indicates the clock of the clock source which is being selected is internally valid.
0: Indicates the clock of the clock which is being selected is internally invalid.
1: Indicates initialization is in progress.
0: ---
are recognized correctly, the delay operation is started and the register is set to ‘1’.
When an error is detected while the input data formats are recognized, the register is
remained ‘0’. The register is set to ‘0’ when the TMG_ERR bit is set to ‘1’ by the
change of the input signal or when the ENBL bit is cleared.
source.
until initialization of the internal DRAM is completed.
This bit is changed each time data is written in each setting register.
output formats. When the ENBL bit is set while this bit is being set, the delay operation
is not started until the interval operation is completed and this bit is cleared.
are ready.
switching the source in the 2-ch mode.
SRC_CHG
Table 30 Operation Status Register Map
BIT6
V
SRC_CLK
BIT5
V
BIT4
0
Description
BIT3
0
CFG_ERS DRAM_RDY
BIT2
V
BIT1
V
FEDL87V5002-01
ML87V5002
2ch or
BIT0
INIT
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V