ml87v5002 Oki Semiconductor, ml87v5002 Datasheet - Page 29

• Manufacturer Part Number: ml87v5002
• Description: Audio Delay Ic With Built-in 2-mbit Dram
• Manufacturer: Oki Semiconductor

OKI Semiconductor
Register Name
Default Value
Error status
DATA_BIT
Register Name
WR
RD
TMG_ERR
BCK_ERR
CFG_ERR
OVRN
UDRN
SUB_ADDRESS=09h(R/W)
TMG_ERR
BIT7
1: This bit is set to ‘1’ when a change of the input timing (the relationship between LRCKI
0: ---
* Even if this bit is ‘1’, the delay operation is started when the ENBL bit is set to ‘1’. This
1: Indicates delay operations are suspended due to any inconsistency in various setting
0: ---
* The delay operation is stopped when this bit is set, regardless of the state of the
1: This bit is set to ‘1’ and the delay operation is stopped when the number of BCK
0: ---
* This bit is cleared once at the time of operation start when the ENBL bit is set to ‘1’. If
* When AUTORSTRT==0, the delay operation is stopped.
* When AUTORSTRT==0, the delay operation is stopped.
1: This bit is set to ‘1’ when the delay buffer overflows due to the period of the input data
0: ---
1: This bit is set to ‘1’ when the delay buffer underflows due to the period of the input
0: ---
V
V
0
Table 33 Descriptions of the Status Register Functions
bit should be cleared by writing ‘0’ to this bit since this bit is not cleared automatically.
input signals are checked again when the initialization of the input signals is performed
and the set register is not consistent with the input signals, the delay operation is
stopped regardless of the state of the AUTORSTRT bit
This bit is cleared by writing ‘0’.
When AUTORSTRT==0, the delay operation is started after the synchronization of
input signals is performed again.
This bit is cleared by writing ‘0’.
When AUTORSTRT==0, the delay operation is started after the synchronization of
input signals is performed again.
This bit is not set to ‘1’ when 0s are output while data equivalent to the delay time is
has not been written in the delay buffer due to the change of the delay register.
This bit is cleared by writing ‘0’.
AUTORSTRT bit. This bit is cleared by writing ‘0’.
values.
and BCKI) is detected after the operation is started, and the delay operation is
stopped.
pulses is less than the set input bit length or less than the set output data length in the
external synchronization mode after the operation is started.
data that is longer than that of the output data.
that is shorter than that of the output data.
CFG_ERR BCK_ERR
BIT6
Table 32 Error Status Register Map
V
V
0
BIT5
V
V
0
OVRN
Description
BIT4
V
V
0
UDRN
BIT3
V
V
0
BIT2
0
BIT1
FEDL87V5002-01
0
ML87V5002
BIT0
0
29/36