mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 106

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
10:8
Bit #
15
14
13
12
7:0
11
7
6
5
4
3
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
Write 1 to count all User cells sent on the TX TDM link N+8.
Write 0 to count the total number of cell sent on the TX TDM link N+8.
Set to 1 to start sending User Cells in IMA mode on link N+8.
Set to 0 to send always Filler and ICP cells in IMA mode
(Note: in non-IMA mode, the control to send User cells is implemented with the UTOPIA
Input Link PHY Enable register).
Coset value. A 0 will generate HEC with Coset value. When 1, Coset is not added.
Cell Scrambling. A 1 enables the scrambling of the cells on the link N+8.
Set to 1 for non-IMA mode and clear to 0 for IMA mode. Select the IMA group number
BEFORE enabling the IMA mode.
Defines IMA group number when the link is configured in IMA mode. Select the IMA group
number BEFORE enabling the IMA mode. When configuring the link in non-IMA mode
after it was in IMA mode, do not change the IMA group number until the link is reported in
non-IMA mode (refer to TX IMA Mode Status Register).
Write 1 to count all User cells sent on the TX TDM link N.
Write 0 to count the total number of cells sent on the TX TDM link N.
Set to 1 to start sending User Cells in IMA mode.
Set to 0 to send continuously Filler and ICP cells in IMA mode
(Note: in non-IMA mode, the control to send User cells is implemented with the UTOPIA
Input Link PHY Enable register).
Coset value. A 0 will generate HEC with Coset value, when 1, Coset is not added.
Cell Scrambling. A 1 enables the scrambling of the cells on the link N.
Set to 1 for non-IMA mode and clear to 0 for IMA mode. Select the IMA group number
BEFORE enabling the IMA mode.
Defines the ICP cell offset of link N. The value of M determines which significant bits are
used as follows:
M = 256; bits 7-0 are used,
M = 128; bits 6-0 are used,
M = 64; bits 5-0 are used,
M = 32; bits 4-0 are used.
0x0318 - 0x031F (8 reg)
1 register per 2 links, link 0 is paired with link 8, link1 with link 9 and so on.
The MSByte contains control the link 8-9 and LSByte control links 0-7
0808
0x0310 - 0x0317 (8 reg)
1 register per 2 links, used in IMA mode only. Link 0 is paired with link 8,
link 1 with link 9, and so on. For MT90222 only groups 0, 1, 2 and 3 are used.
physical link #
Table 74 - TX ICP Cell Offset Registers (continued)
Table 75 - TX Link Control Registers
Zarlink Semiconductor Inc.
MT90222/3/4
106
Description
Description
Data Sheet