mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 35

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

Specification and are pre-loaded in the MT90222/3/4 following a reset. The TX Cell RAM Control (0x0080) register
can be used to re-initialize the TX Cell RAM.
2.2.1
The internal TX Cell RAM can hold up to 128 cells. The following 10 cells are reserved for MT90222/3/4 operation:
•
•
•
The remaining 118 cells can be assigned to any of the 40 TX FIFOs. The TX FIFOs are divided into 24 TX UTOPIA
FIFOs and 16 TX Link FIFOs. The MT90222/3/4 implements one TX UTOPIA FIFO for each link when used in TC
mode and one for each IMA Group, totalling up to 24 TX UTOPIA FIFOs. Each TX UTOPIA FIFO is associated with
one TX UTOPIA Address. Please refer to section 5.0 "UTOPIA Interface Operation" for more details.
In addition, for each link to be used in IMA mode, an internal TX Link FIFO is utilized. These TX Link FIFOs hold the
cell streams that are to be sent on each TX serial port. There is a total of 16 TX Link FIFOs and their size is
programmed on a per group basis using the TX IMA Control (0x0321-0x0324) register. When a link is used in TC
mode, its corresponding TX Link FIFO is disabled and the TX Link UTOPIA FIFO is used.
The MT90222 and MT90223 support a subset of the 16 links and only the registers corresponding to available links
are meaningful.
TX IMA UTOPIA FIFO Length Definition (0x0093-0x0096) registers are used to set the size of the IMA FIFO. A
maximum of 6 cells can be assigned to any single FIFO. The size of unused TX IMA UTOPIA FIFOs should be set
to zero. The recommended size for the IMA Group TX UTOPIA FIFO is 2.
In IMA Mode, the ATM User Cells are first placed in the TX IMA UTOPIA FIFO and then transferred, by the internal
round robin scheduler, to the proper TX Link FIFO.
The TX IMA Control (0x0321-0x0324) registers are used to set the size of the internal TX Link FIFO for a link in
IMA mode. An upper and lower level limit must be set for the internal TX Link FIFO.
The recommended upper limit value for the internal TX Link FIFO is five and the recommended lower limit is one
when operating in ITC clocking mode. When operating in CTC mode, the recommended upper limit value for the
internal TX Link FIFO is six and the recommended lower limit is one. In the case where CTC mode is used and
when the ICP cells on all the links are sent with the same ICP cell offset and when carrying a CBR-type traffic, an
upper value of 7 may be required.
In TC Mode, the ATM User Cells are queued in the TX Link UTOPIA FIFO (0x008B - 0x0092) until sent over the
serial link.
2.3
ATM cell octet byte alignment conforms to ITU G.804 recommendations for T1 or E1 framer parallel to serial format
conversion.
The TDM TX Link Control Register (0x0600-0x060F) and TDM RX Link Control Register (0x0700-0x070F)
registers are used to select the serial mode of operation. Additionally, the serial links can operate at rates up to
2.5 Mb/s individually, or up to 5.0 Mb/s when paired or 10 Mb/s when grouped in fours. Refer to Description of the
TDM interface for more details.
one ICP cell for each IMA Group for a total of eight cells
one common Filler Cell used in IMA mode
one Idle Cell used in TC mode
Parallel to Serial TDM Interface
TX Cell RAM and TX FIFO Length
Zarlink Semiconductor Inc.
MT90222/3/4
35
Data Sheet