mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 71

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

an overflow condition. When enabled, the bits in this status register reflect any overflow condition reported by the
IRQ IMA Overflow Status (0x0420-0x0427) registers.
The IRQ IMA Group Overflow Enable (0x040B) register is used to enable any overflow conditions for a specific
IMA Group. Each of the four bits correspond to one of the eight IMA Groups. A value of ’1’ enables the report of the
overflow condition to the upper IRQ levels.
6.2.5
There are five possible sources of overflow conditions that can be reported for each IMA Group.
The IRQ IMA Overflow Status (0x0420-0x0427) register captures (latches) the overflow condition from any of the
four counters associated with the UTOPIA TX I/F when the TDM link is used in IMA mode. It also latches when an
overflow condition occurs in the RX UTOPIA FIFO associated to a TDM link when in IMA mode.
The status bit is cleared by overwriting it with a 0. Reading the registers or writing a ’1’ to these registers will not
change the content of the registers. A counter generates an interrupt request, if not masked, when the counter
overflows (i.e., starts over from 0 after reaching the maximum counter value - refer to Section 6.1 for more details
on the operation of the counters). An interrupt request can also be generated, if not masked, when an overflow
condition is detected in the UTOPIA RX FIFO associated with an IMA Group.
There is one enable register used to enable the generation of an interrupt by the overflow condition of the RX
UTOPIA FIFO associated with an IMA Group. This is the RX UTOPIA IMA Group FIFO Overflow IRQ Enable
(0x040C) register.
6.3
6.3.1
Since the MT90222/3/4 and microprocessor operate from two different clock sources, access to a MT90222/3/4
register is asynchronous. Data is synchronized between the MT90222/3/4 and the microprocessor using either direct
or indirect (synchronized) methods of access.
The direct method is used during a read access whenever data does not change or data changes do not represent
any problem. There is no register that clears status bits upon a read access. A write action is always required to clear
a status bit.
The indirect method is identified with ’S’ (indirect and need to synchronize with a ready bit) whereas the direct access
is identified with a ’D’ in the register tables.
6.3.2
Direct access registers can be written or read directly by the microprocessor, without having to use other registers.
Upon a write access to the MT90222/3/4 internal registers, the data is stored in an internal latch and transferred to
the destination register within 2.5 system clock cycles (50 nsec at 50 MHz). No specific action is required if the
microprocessor provides at least 50 nsec (with Chip Select signal inactive) between 2 consecutive write accesses
or between a write and a read back of the same register. If the microprocessor is faster, then consecutive accesses
must be inhibited or wait state(s) introduced (this option is available on most MCUs).
6.3.3
Indirect access registers cannot be accessed directly by the microprocessor. The value is transferred back and forth
using registers which hold a copy of the information (data) and internal address of the register. This is required to
stabilize the read value. Consider for example the transfer of a TX ICP cell that requires almost 200 system clock
cycles. A dedicated ready bit which can optionally generate an interrupt is implemented for this type of transfer.
Microprocessor Interface Block
IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers
Access to the Various Registers
Direct Access
Indirect Access
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MT90222/3/4
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Data Sheet