zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet

zl50018gag2

Manufacturer Part Number

zl50018gag2

Description

2 K Digital Switch With Enhanced Stratum 3 Dpll

Manufacturer

Zarlink Semiconductor

Datasheet

1.ZL50018GAG2.pdf (136 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ZL50018GAG2

Manufacturer:

TECCOR

Quantity:

5 600

Current page: 1 of 136
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REF_FAIL0

REF_FAIL1

REF_FAIL2

REF_FAIL3

MODE_4M0

MODE_4M1

Features

•

STi[31:0]

OSC_EN

2048 channel x 2048 channel non-blocking digital

Time Division Multiplex (TDM) switch at 8.192

and 16.384 Mbps or using a combination of ports

running at 2.048, 4.096, 8.192 and/or

16.384 Mbps

32 serial TDM input, 32 serial TDM output

streams

Integrated Digital Phase-Locked Loop (DPLL)

exceeds Telcordia GR-1244-CORE Stratum 3

specifications

Output clocks have less than 1 ns of jitter (except

for the 1.544 MHz output)

DPLL provides holdover, freerun and jitter

attenuation features with four independent

reference source inputs

Programmable key DPLL parameters (filter

corner frequency, locking range, auto-holdover

REF3

REF0

REF1

REF2

CKi

FPi

DD_CORE

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

S/P Converter

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Input Timing

OSC

DPLL

DD_IO

Figure 1 - ZL50018 Functional Block Diagram

DD_COREA

Microprocessor Interface

Zarlink Semiconductor Inc.

Internal Registers &

Connection Memory

Data Memory

DD_IOA

•

hysteresis range, phase slope, lock detector

range)

Exceptional input clock cycle to cycle variation

tolerance (20 ns for all rates)

Output streams can be configured as bi-

directional for connection to backplanes

ZL50018GAC

ZL50018QCC

ZL50018QCG1

ZL50018GAG2

2 K Digital Switch with Enhanced

RESET

**Pb Free Tin/Silver/Copper

P/S Converter

Ordering Information

Output Timing

Test Port

Output HiZ

*Pb Free Matte Tin

Control

-40°C to +85°C

ODE

256 Ball PBGA

256 Lead LQFP

256 Lead LQFP*

256 Ball PBGA**

Stratum 3 DPLL

Trays

Trays, Bake &

Drypack

Trays, Bake &

Drypack

Data Sheet

STio[31:0]

STOHZ[15:0]

FPo[3:0]

CKo[5:0]

FPo_OFF[2:0]

ZL50018

November 2006

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