zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 73

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

Note: The default value is ±56 ppm (’h099F/CFN = 56 ppm).
15 - 13
15 - 14
Reset Value: 099F
Reset Value: 0002
External Read/Write Address: 0049
External Read/Write Address: 004A
12 - 0
11 - 8
Bit
Bit
13
12
15
15
0
0
14
14
0
SRL12 - 0
0
FLF_QS
FLC3 - 0
Unused
Unused
Name
Name
BLM
H
H
BLM
13
(see Note)
13
(see Note)
0
FLF_
SRL
Reserved. In normal functional mode, these bits MUST be set to zero.
Slew Rate Limit Bits: The binary value of these bits defines the maximum rate of DPLL
phase change (phase slope), where the phase represents difference between the input
reference and output feedback clock. Defined in same units as CFN (unsigned).
Reserved. In normal functional mode, these bits MUST be set to zero.
Bypass Limiter Bit: When this bit is high, the DPLL slew rate limiter is bypassed
(ignored). In combination with FLF_QS, FLC3 - 0, FFL3 - 0 and LPF3 - 0 bits, causes fast
locking of the DPLL output clocks to the selected reference.
When this bit is low, the DPLL performs normal lock following the slew rate limit defined
in the slew rate limit register (SRLR).
Fast Lock Frequency Quick Stabilization Bit: This bit is used to control speed of
internal frequency stabilization.
When this bit is high, the DPLL internal frequency will quickly stabilize to the appropriate
value, allowing very fast storage of holdover frequency value.
When this bit is low, the internal frequency value will be reached over normal locking time
(i.e. <100 seconds), and some extra jitter on output clocks can be expected.
It is recommended to set this bit if fast locking functionality is desired.
When the BLM bit is low, this bit is ignored.
Fast Lock Control Bits: Value of these bits (unsigned) control stability of frequency
when FFL3 - 0 bits of this register are used. Larger values result in faster locking and are
recommended for reference clocks with small jitter, while smaller values are
recommended for references with presence of significant jitter.
QS
12
12
12
Table 39 - Bandwidth Control Register (BWCR) Bits
H
H
Table 38 - Slew Rate Limit Register (SRLR) Bits
SRL
FLC
11
11
11
3
SRL
FLC
10
10
10
2
SRL
FLC
9
9
9
1
Zarlink Semiconductor Inc.
ZL50018
SRL
FLC
8
8
8
0
73
SRL
FFL
7
7
7
3
Description
Description
SRL
FFL
6
6
6
2
SRL
FFL
5
5
5
1
SRL
FFL
4
4
4
0
SRL
LPF
3
3
3
3
SRL
LPF
2
2
2
2
Data Sheet
SRL
LPF
1
1
1
1
SRL
LPF
0
0
0
0