zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 32

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

7.4
In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers
better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the
serial data output pins.
By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the
output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the
Stream Output Control Register 0 - 31 (SOCR0 - 31). For all streams running at any data rate except 16.384 Mbps
the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. For streams operating at 16.384 Mbps, the
fractional bit advancement can be set to either 0 or 1/2 bit.
STio[n]
STo[n]FA1-0 = 10
(2, 4 or 8)
STo[n]FA1-0 = 01
(16 Mbps)
STio[n]
STo[n]FA1-0 = 11
(2, 4 or 8 Mbps)
FPi
STio[n]
STo[n]FA1-0 = 00
(Default)
STio[n]
STo[n]FA1-0 = 01
(2, 4 or 8 Mbps)
Fractional Output Bit Advancement Programming
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
2
1
Last Channel
1
Last Channel
Last Channel
Last Channel
1
1
0
Zarlink Semiconductor Inc.
0
ZL50018
0
0
32
7
7
Channel 0
7
Fractional Bit Advancement = 1/4 Bit
Channel 0
Fractional Bit Advancement = 1/2 Bit
Fractional Bit Advancement = 3/4 Bit
7
Channel 0
Channel 0
6
6
6
6
5
5
5
5
4
4
Data Sheet
4