zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 44

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

14.0
14.1
The ZL50018 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50018
to synchronize off a low cost DPLL when it is in either Divided Slave mode or Multiplied Slave mode.
14.2
The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the
input clock that the DPLL must accept without making cycle slips or losing lock. The lower the jitter frequency, the
larger the jitter acceptance. For jitter frequencies below a tenth of the cut-off frequency of the DPLL's jitter transfer
function, it safely can be said that any provided input jitter will be followed by the DPLL. The maximum value of jitter
tolerance for the DPLL is ±1023 UI
14.3
The corner frequency (-3 dB) of the DPLL is programmable through LPF (bits 3 - 0) in the Bandwidth Control
Register (BWCR) from 0.475 Hz to 15.5 kHz, in 16 steps. Stratum 3 requires a corner frequency of maximally 3 Hz.
The default corner frequency is 1.9 Hz.
15.0
15.1
To determine if the DPLL is locked to the input clock, a lock detector monitors the phase value output of the phase
detector, which represents the difference between input reference and output feedback clock. If the phase value is
below a certain threshold for a certain interval, the DPLL is pronounced locked to the input clock. The monitoring is
done in intervals of 4ms. The lock detector threshold and the interval are programmable by the user through the
Lock Detector Threshold Register (LDTR) and the Lock Detector Interval Register (LDIR) respectively. See
Table 36 on page 72 and Table 37 on page 72 for the bit descriptions of the Lock Detector Threshold Register
(LDTR) and Lock Detector Interval Register (LDIR) respectively. The value of the Lock Detector Threshold Register
(LDTR) should be programmed with respect to the maximum expected jitter frequency and amplitude on the
selected input references.
The lock status can be monitored through the Reference Change Status Register (RCSR). See Table 41 on
page 76 for the bit description of the Reference Change Status Register (RCSR).
15.2
Several standards require that the output clock of the DPLL may not move in phase more than a certain amount. In
order to meet those standards, a special circuit maintains the phase of the DPLL output clock during reference and
mode rearrangements. The total output phase change or Maximum Timing Interval Error (MTIE) during
rearrangements is less than 31 ns per rearrangement, exceeding Stratum 3 requirements. After a large number of
reference switches, the accumulated phase error can become significant, so it is recommended to use MTIE reset
in such situations, to realign outputs to the nearest edge of the selected reference. The MTIE reset can be
programmed by setting MTR (bit 7) in the Reference Change Control Register (RCCR), as described in Table 40 on
page 75.
15.3
Besides total phase change, standards also require a certain rate of the phase change of the output clock. The
phase alignment speed is programmable by the user through a value in the Slew Rate Limit Register (SRLR) as
described in Table 38 on page 73. Stratum 3 requires that the phase alignment speed not exceed 81 ns per
Input Clock Cycle to Cycle Timing Variation Tolerance
Input Jitter Acceptance
Jitter Transfer Function
Lock Detector
Maximum Time Interval Error (MTIE)
Phase Alignment Speed (Phase Slope)
Jitter Performance
DPLL Specific Functions and Requirements
p-p
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Zarlink Semiconductor Inc.
ZL50018
44
Data Sheet