zl50064 Zarlink Semiconductor, zl50064 Datasheet
zl50064
Related parts for zl50064
zl50064 Summary of contents
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... Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. 16K-Channel Digital Switch with High Jitter Tolerance, Single Rate ( 16Mbps), and 64 Inputs and 64 Outputs ZL50062GAC ZL50064QCC • Per-stream bit delay for Local and Backplane input streams • Per-stream advancement for Local and Backplane output streams • ...
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... I/O supply voltage • 5V tolerant inputs, outputs and I/Os Applications • Central Office Switches (Class 5) • Media Gateways • Class-independent switches • Access Concentrators • Scalable TDM-Based Architectures • Digital Loop Carriers ZL50062/4 2 Zarlink Semiconductor Inc. Data Sheet ...
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... The ZL50062 and ZL50064 are two different packages of the same device. They have the same functionality except that ZL50064 does not have 16.384MHz output clock and frame pulse (C16o and FP16o) due to package differences. The ZL50062/4 has two data ports, the Backplane and the Local port. The device can operate at four different data rates, 2 ...
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... Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ZL50062/4 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Advancement Registers (LOAR0 to LOAR31 13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0 13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31 13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0 13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.8 Bit Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.9 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ZL50062/4 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50062/4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50064 LQFP Connections (256 LQFP, 28mm x 28mm) Pin Diagram (as viewed through top of package Figure 3 - ZL50062 PBGA Connections (256 PBGA, 17mm x 17mm) Pin Diagram (as viewed through top of package Figure 4 - 16,384 x 16,384 Channels (16Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5 - 8,192 x 8,192 Channels (16Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration ...
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... Table 20 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 21 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 22 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 23 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 24 - Bit Rate Register (BRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 25 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ZL50062/4 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... BSTi22 BSTi21 254 BSTi23 BSTi24 256 Figure 2 - ZL50064 LQFP Connections (256 LQFP, 28mm x 28mm) Pin Diagram ZL50062/4 170 168 166 164 162 160 158 156 154 152 150 148 146 144 256 PIN LQFP (TOP VIEW) ...
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... D11 D10 D9 D8 C16o FP16o BSTi26 D15 D14 D13 D12 FP8o FP8i BSTi31 IC_GND IC_GND IC_GND IC_GND C8i C8o (as viewed through top of package) 9 Zarlink Semiconductor Inc. Data Sheet IC_ IC_ IC_ IC_ IC_ OPEN OPEN OPEN OPEN OPEN TMS ...
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... Pin Description ZL50064 Package Pin Name Coordinates Coordinates (256-pin LQFP) Device Timing C8i 37 FP8i 43 C8o 41 FP8o 42 C16o NA ZL50062/4 ZL50062 Package (256-ball PBGA) T10 Master Clock (5V Tolerant Schmitt-Triggered Input). This pin accepts an 8.192MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register ...
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... Pin Description (continued) ZL50064 Package Pin Name Coordinates Coordinates (256-pin LQFP) FP16o NA Backplane and Local Inputs BSTi0-15 228, 229, K1, K2, K3, 230, 231, L3, L4, M1, 232, 233, M2, M3, M4, 234, 235, N1, N2, N3, 236, 238, 237, 240, 239, 242, 241, 244 BSTi16-31 248, 250, N5, P1, P2, ...
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... Pin Description (continued) ZL50064 Package Pin Name Coordinates Coordinates (256-pin LQFP) Backplane and Local Outputs and Control ODE 149 BORS 223 BSTo0-15 182, 181, B1, B2, B3, B4, C1, C2, 184, 183, C3, C4, D1, 186, 185, D2, D3, D4, 188, 187, E1, E2, E3, 191, 192, 193, 194, 195, 197, ...
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... Pin Description (continued) ZL50064 Package Pin Name Coordinates Coordinates (256-pin LQFP) LORS 84 LSTo0-15 130, 129, 128, 127, 126, 125, 121, 118, 119, 116, 117, 114, 115, 113, 108, 107 LSTo16-31 106, 105, 104, 103, 102, 101, 98, 97, 96, 95, 94, 93, 92, 91, 86, 85 ...
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... Pin Description (continued) ZL50064 Package Pin Name Coordinates Coordinates (256-pin LQFP) CS 151 DS 157 R/W 152 DTA 150 RESET 148 JTAG Control Signals TCK 143 TMS 147 TDi 145 TDo 146 ZL50062/4 ZL50062 Package (256-ball PBGA) A8 Chip Select (5V Tolerant Input). Active LOW input used by the microprocessor to enable the microprocessor port access ...
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... Pin Description (continued) ZL50064 Package Pin Name Coordinates Coordinates (256-pin LQFP) TRST 144 Power and Ground Pins V 7, 20, 34, 48, E5, E6, E11, DD_IO E12, F5, F12, 67, 87, 99, G5, G12, H5, 109, 120, H12, L5, L12, 134, 153, 173, 189, 198, 211, 224, 243 V 12, 23, 36, ...
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... Pin Description (continued) ZL50064 Package Pin Name Coordinates Coordinates (256-pin LQFP) Unused Pins NC IC_OPEN 131, 132, A9, A10, A11, 137, 138, 139, 140, 141, 142 IC_GND 32, 33, 158, D6, D7, D8, 159, 160, 161 D9, T6, T7, ZL50062/4 ZL50062 Package (256-ball PBGA) M11 No Connects. These pins are not used and can be tied HIGH, LOW, or left unconnected ...
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... Local side. Note that some or all of the output channels on one side can come from the other side, e.g., Backplane input to Local output switching. ZL50062/4 BSTo0-31 32 streams LSTo0-31 32 streams ZL50062/64 LSTo0-31 32 streams LSTi0-31 32 streams ZL50062/64 17 Zarlink Semiconductor Inc. Data Sheet OUTPUT LOCAL ...
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... Local input to Local output streams BSTi0-31 LSTi0-15 BSTo0-31 LSTo0-15 Total 48 streams input and 48 streams output Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration ZL50062/4 ZL50062/64 12K by 4K 12K by 12K 12K Total 16 streams input and 16 streams output 18 Zarlink Semiconductor Inc. Data Sheet LSTi16-31 LSTo16-31 ...
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... Local Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local Connection Memory. Refer to Section 8.1, Local Connection Memory, and Section 11.3, Local Connection Memory Bit Definition for more details. ZL50062/4 19 Zarlink Semiconductor Inc. Data Sheet ...
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... In addition, the ZL50062 device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to the output ports. The ZL50064 only provides FP8o and C8o outputs. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master frame pulse (FP8i). The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register bit, COPOL ...
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... Channel Channel Channel Channel 0 6 Channel 0 1 Channel 0 7 Channel Zarlink Semiconductor Inc. Data Sheet Channel 255 Channel 255 Channel 127 Channel 127 ...
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... The ZL50062 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. The ZL50064 only generates one frame pulse output, FP8o. There is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during Frame N is output during Frame N+2 ...
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... Refer to Figure 9 and Figure 10 for Input Bit Delay Timing at 16Mbps and 8Mbps data rates, respectively. Refer to Figure 10 for Input Sampling Point Selection Timing at 8Mbps data rates. ZL50062/4 ), and the sampling point was optimized Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Delay, 1 Ch0 Ch255 Ch255 Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Ch1 Ch1 Ch1 2 ...
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... Figure 11. ZL50062/4 Ch127 Ch0 sample at 3/4 point Ch127 Ch0 sample at 3/4 point Ch127 Ch0 sample at 3/4 point Ch127 Ch0 sample at 2/4 point Data Rate of 8Mbps 25 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit 0 Bit 7 LE/BE OSB (Local / (Control Backplane Register bit) Connection Memory bit Zarlink Semiconductor Inc. Data Sheet Ch0 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Ch0 Bit 4 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Bit 4 LORS/BORS LSTo0-31/ (input pin) BSTo0-31 0 HIGH ...
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... Output Stream Output Channel Data Rate Number (n) 2Mbps 4Mbps 8Mbps 0 to 127 16Mbps 0 to 255 27 Zarlink Semiconductor Inc. Data Sheet LORS/BORS LSTo0-31/ (input pin) BSTo0-31 1 HI-Z 0 HIGH 1 HI-Z X ACTIVE (HIGH or LOW) ...
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... Frame N+1 Data Frame N+1 Frame N+2 Frame N+3 Frame N+1Data Frame N+2 Data Frame N+3 Data 2 Frames + ( Frame N-1 Data Frame N Data Frame N+1 Data 28 Zarlink Semiconductor Inc. Data Sheet Frame N+4 Frame N+5 Frame N+4 Data Frame N+5 Data Frame N+2 Data Frame N+3 Data Frame N+4 Frame N+5 Frame N+4 Data Frame N+5 Data Frame N+2 Data ...
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... RESET pin; this delay is required for determination of the frame pulse format. ZL50062/4 supply (nominally +3.3V established before the DD_IO supplies (nominally +1.8V). The V DD_PLL supply by more than 0.3V. DD_IO 29 Zarlink Semiconductor Inc. Data Sheet and V supplies may be DD_CORE ...
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... The Control Register bits MS[2:0] must be set to 001 to select the Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 6.0, Microprocessor Port, and Section 13.1, Control Register (CR) for details on microprocessor port access. ZL50062/4 RESET de-assertion Figure 15 - Hardware RESET De-assertion 30 Zarlink Semiconductor Inc. Data Sheet ...
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... Zarlink Semiconductor Inc. Data Sheet Source Channel No. Bits[7:0] legal values 0:31 Bits[7:0] legal values 0:63 Bits[7:0] legal values 0:127 Bits[7:0] legal values 0:255 ...
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... Test Data Register to operate while the instruction is current, and to define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please refer to Figure 27 for JTAG test port timing. ZL50062/4 32 Zarlink Semiconductor Inc. Data Sheet when not DD_IO ...
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... Manufacturer ID, Bits <11:1>:0001 0100 101 Header, Bit <0> (LSB):1 10.3 Boundary Scan Description Language (BSDL) File A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149.1 test interface. 11.0 Memory Address Mappings When the most significant bit, A14, of the address bus is set to ’1’, the microprocessor performs an access to one of the device’ ...
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... Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-31) in place of data defined by the Source Control, Stream and Channel Address bits. ZL50062/4 Description Table 8 - Local Data Memory (LDM) Bits Description 34 Zarlink Semiconductor Inc. Data Sheet ...
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... When LOW, the channel is in Connection Mode (data to be output on channel originated in Backplane or Local Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Backplane Connection Memory). Table 11 - BCM Bits for Source-to-Backplane Switching ZL50062/4 Description Description 35 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Advancement Register 0 - 31, LOAR0 - 00A3 - 00C2 Backplane Output Advancement Register 0 - 31, BOAR0 - 014D Memory BIST Register, MBISTR H 1001 Bit Rate Register, BRR H 3FFF Device Identification Register, DIR H Table 12 - Address Map for Registers (A14 = 0) ZL50062/4 Description Register 36 Zarlink Semiconductor Inc. Data Sheet ...
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... When HIGH, the output clock is inverted. This applies to both the 8MHz (C8o) and 16MHz (C16o) output clocks. ZL50062/4 Description , the Frame Boundary Discriminator can handle both low B , the Frame Boundary Discriminator is set to handle lower B Table 13 - Control Register Bits 37 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 13 - Control Register Bits (continued) ZL50062/4 Description ODE Pin OSB bit BSTo0-31, LSTo0- Zarlink Semiconductor Inc. Data Sheet Disabled Disabled Enabled ...
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... Frame Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (d) Frame Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 16 - Frame Boundary Conditions, ST-BUS Operation Zarlink Semiconductor Inc. Frame Boundary 39 Data Sheet ...
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... FP8i (g) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (h) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 17 - Frame Boundary Conditions, GCI-Bus Operation Zarlink Semiconductor Inc. ZL50062/4 Frame Boundary 40 Data Sheet ...
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... BPE 0 Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 s, upon completion of programming. Set LOW to abort the programming operation. Table 14 - Block Programming Register Bits ZL50062/4 Description 41 Zarlink Semiconductor Inc. Data Sheet ...
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... When SMPL_MODE = LOW, the binary value of these bits refers to the input bit and fractional bit delay value ( When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point ( refer to the integer bit delay value ( bits). 42 Zarlink Semiconductor Inc. Data Sheet LID[4: ...
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... Zarlink Semiconductor Inc. Data Sheet LID[4: SMPL_MODE = HIGH Input Data Input Data Sampling Bit Delay Point 0 (Default) 3/4 0 4/4 0 1/4 0 2/4 1 3/4 1 4/4 ...
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... When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point ( refer to the integer bit delay value ( bits). 44 Zarlink Semiconductor Inc. Data Sheet SMPL_MODE = HIGH Input Data Input Data Sampling Bit Delay Point 7 ...
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... Zarlink Semiconductor Inc. Data Sheet BID[4: SMPL_MODE = HIGH Input Data Input Data Sampling Bit Delay Point 0 (Default) 3/4 0 4/4 0 1/4 0 2/4 1 3/4 1 4/4 1 ...
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... Reset Name Value Reserved 0 Reserved Must be set to 0 for normal operation LOA[1:0] 0 Local Output Advancement Value LOA1 0 (Default) 46 Zarlink Semiconductor Inc. Data Sheet SMPL_MODE = HIGH Input Data Input Data Sampling Bit Delay Point 6 2/4 7 3/4 7 4/4 7 1/4 7 2/4 Description Corresponding ...
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... Must be set to 0 for normal operation Table 23 - Memory BIST Register (MBISTR) Bits ZL50062/4 Reset Name Value Reserved 0 Reserved Must be set to 0 for normal operation BOA[1:0] 0 Backplane Output Advancement Value BOA1 0 (Default) Description 47 Zarlink Semiconductor Inc. Data Sheet Description Corresponding Advancement Bits BOA0 ...
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... Local Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Local Connection Memory BIST sequence (indicated by assertion of BISTCCL). A HIGH indicates Pass, a LOW indicates Fail. Table 23 - Memory BIST Register (MBISTR) Bits (continued) ZL50062/4 Description 48 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Rate of all ST-BUS Streams Table 24 - Bit Rate Register (BRR) Bits 0 Reserved Will read 0 in normal operation 0000 Revision Control Bits 0 Reserved Will read 0 in normal operation 110 Device ID 49 Zarlink Semiconductor Inc. Data Sheet 2.048Mbps 4.096Mbps 8.192Mbps 16.384Mbps Description ...
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... ZL50062/4 Symbol Min V -0.5 DD_CORE V -0.5 DD_IO V -0.5 DD_PLL V -0 -0.5 I_5V Sym Min Typ T - 3.0 3.3 DD_IO V 1.71 1.8 DD_CORE V 1.71 1.8 DD_PLL I_5V 50 Zarlink Semiconductor Inc. Data Sheet Max Units 2.5 V 5 DD_IO +0.5 7 1.5 W +125 C Max Units +85 C 3.6 V 1. DD_IO 5.5 V ...
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... BL I 200 PU I 200 2 0 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions mA Static I and DD_Core PLL current mA Applied clock C8i = 8.192 MHz A Static I DD_IO mA I with all output AV streams at max. data rate unloaded < ...
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... FPFBF8_122 t 117 122 FBFPF8_244 FBFPF8_122 t 117 122 OCP8 OCH8 OCL8 rOC8 fOC8 52 Zarlink Semiconductor Inc. Data Sheet Conditions 3.0V < V < 3.6V DD_IO 3.0V < V < 3.6V DD_IO 3.0V < V < 3.6V DD_IO Max Units Notes 350 ns 220 110 ns 60 110 ns 60 124 ...
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... FPFBF16_122 FPFBF16_61 FBFPF16_122 FBFPF16_61 OCP16 OCH16 OCL16 rOC16 t fOC16 53 Zarlink Semiconductor Inc. Data Sheet Max Units Notes 127 ns FPW =1 FPW =60pF FPW =1 FPW FPW =1 FPW =60pF ...
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... Figure 18 - Input and Output Clock Timing Diagram for ST-BUS ZL50062/4 t IFPW244 t IFPH244 t IFPW122 t t IFPS122 IFPH122 t t ICH ICP t rIC t OFBOS t OFPW8_244 t FBFPF8_244 t OFPW8_122 t t FBFPF8_122 FPFBF8_122 t t OCH8 OCP8 t t OFPW16_122 t t FPFBF16_122 FBFPF16_122 t OFPW16_61 t FBFP16_61 t rOC16 54 Zarlink Semiconductor Inc. Data Sheet t fIC t rOC8 fOC8 t OCP16 t fOC16 ...
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... Figure 19 - Input and Output Clock Timing Diagram for GCI-Bus ZL50062/4 t IFPW244 t IFPS244 t IFPW122 t t IFPS122 IFPH122 t t ICP ICH t rIC t OFBOS t OFPW8_244 t FPFBF8_244 t OFPW8_122 t t FBFPF8_122 FPFBF8_122 t t OCP8 OCH8 t rOC8 t OFPW16_122 t t FPFBF16_122 FBFPF16_122 t OFPW16_61 t FBFP16_61 t fOC16 55 Zarlink Semiconductor Inc. Data Sheet t IFPH244 t fIC t FBFPF8_244 t fOC8 t OCP16 t rOC16 ...
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... SIH4 t 2 SIH2 t 7 9.5 OFBOS t 4.5 SOD16 t 4.5 SOD8 t 4.5 SOD4 t 4.5 SOD2 56 Zarlink Semiconductor Inc. Data Sheet Units Notes ns With SMPL_MODE = 0 (3/4-bit sampling) and zero offset. ns With respect to Min. Input Data Sampling Point ns With respect to Max. Input Data Sampling Point =50pF L These numbers ...
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... OFBOS t SOD8 Bit7 Bit6 Bit5 Bit4 Ch0 Ch0 Ch0 Ch0 t SOD4 Bit6 Bit7 Ch0 Ch0 t SOD2 Bit7 Ch0 57 Zarlink Semiconductor Inc. Data Sheet Bit5 Bit4 Ch0 Ch0 Bit6 Ch0 Bit2 Bit1 Bit3 Ch0 Ch0 Ch0 Bit5 Bit4 Ch0 Ch0 Bit6 ...
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... Note *: CK_int is the internal clock signal of 131.072MHz Figure 21 - ST-BUS Local/Backplane Data Timing Diagram (16Mbps) ZL50062/4 t IDS16 t SIS16 t SIH16 Bit7 Bit0 Ch0 Ch255 t OFBOS t SOD16 Bit0 Bit7 Ch0 58 Zarlink Semiconductor Inc. Data Sheet Bit6 Bit5 Ch0 Ch0 Bit5 Bit6 Ch0 Ch0 ...
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... OFBOS t SOD8 Bit0 Bit1 Bit2 Bit3 Ch0 Ch0 Ch0 Ch0 t SOD4 Bit0 Bit1 Ch0 Ch0 t SOD2 Bit0 Ch0 59 Zarlink Semiconductor Inc. Data Sheet Bit2 Bit3 Ch0 Ch0 Bit1 Ch0 Bit5 Bit6 Bit4 Ch0 Ch0 Ch0 Bit2 Bit3 Ch0 Ch0 Bit1 ...
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... L/BSTo0-31 Bit7 Ch255 16.384Mbps Note *: CK_int is the internal clock signal of 131.072MHz Figure 23 - GCI-Bus Local/Backplane Data Timing Diagram (16Mbps) ZL50062/4 t IDS16 t SIS16 t SIH16 Bit0 Bit1 Ch0 Ch0 t OFBOS t SOD16 Bit0 Bit1 Ch0 Ch0 60 Zarlink Semiconductor Inc. Data Sheet Bit2 Ch0 Bit2 Ch0 ...
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... DZ Valid Data HiZ t ZD Valid Data HiZ t t ODE ODZ Valid Data STo Hi-Z Hi-Z Figure 25 - Output Driver Enable (ODE) 61 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns R =1k, C =50pF, See Note =1k, C =50pF, See Note =1k, C ...
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... ZL50062/4 16.384Mbps Data Rate Units Jitter Tolerance 1200 ns 1200 ns 150 ns 110 Zarlink Semiconductor Inc. Data Sheet ...
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... RDS 12 t 4.5 RDH t 9 WDS t 9 WDH t AKD AKH , with timing corrected to cancel time taken to discharge L 63 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Memory Read Register Read ns C =60pF =60pF Note 1 ...
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... D0-D15 READ D0-D15 WRITE DTA Figure 26 - Motorola Non-Multiplexed Bus Timing ZL50062/4 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t RDS t AKD 64 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH RDH WDH V TT ...
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... Typ t 100 TCKP t 80 TCKH t 80 TCKL t 10 TMSS t 10 TMSH t 20 TDIS t 60 TDIH t TDOD t 200 TRSTW t t TCKL TCKH t TCKP t TMSH t TDIH t TDOD 65 Zarlink Semiconductor Inc. Data Sheet Max Units Notes =30pF TRSTW ...
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... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...