zl50064 Zarlink Semiconductor, zl50064 Datasheet - Page 47

• Manufacturer Part Number: zl50064
• Description: 16 K Channel Digital Switch With High Jitter Tolerance, Single Rate 2, 4, 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

13.6
Addresses 00A3
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR31) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. The possible adjustment is -2 (15ns), -4 (31ns) or -6
(46ns) cycles of the internal system clock (131.072MHz).
The BOAR0 to BOAR31 registers are configured as follows:
13.6.1
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
13.7
Address 014D
The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to
start MBIST: the first with only Bit 12 (LV_TM) set HIGH (i.e. 1000h); the second with Bit 12 maintained HIGH but
with the required start bit(s) also set HIGH.
The MBISTR register is configured as follows:
15:13
Bit
(where n = 0 to 31)
Backplane Output Advancement Registers (BOAR0 - BOAR31)
Memory BIST Register
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
Reserved
BOARn Bit
Name
15:2
H
1:0
.
H
Table 22 - Backplane Output Advancement (BOAR) Programming Table
to 00C2
Table 21 - Backplane Output Advancement Register (BOAR) Bits
Reset
Value
Backplane Output Advancement
0
H
Clock Rate 131.072 MHz
Table 23 - Memory BIST Register (MBISTR) Bits
-2 cycles (~15ns)
-4 cycles (~31ns)
-6 cycles (~46ns)
Reserved
Must be set to 0 for normal operation
0 (Default)
Reserved
BOA[1:0]
Name
Zarlink Semiconductor Inc.
ZL50062/4
Reset
Value
0
0
47
Reserved
Must be set to 0 for normal operation
Backplane Output Advancement Value
Description
BOA1
Advancement Bits
0
0
1
1
Corresponding
Description
BOA0
0
1
0
1
Data Sheet