zl50064 Zarlink Semiconductor, zl50064 Datasheet - Page 46

• Manufacturer Part Number: zl50064
• Description: 16 K Channel Digital Switch With High Jitter Tolerance, Single Rate 2, 4, 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

13.5
Addresses 0083
Thirty-two Local Output Advancement Registers (LOAR0 to LOAR31) allow users to program the output
advancement for output data streams LSTo0 to LSTo31. The possible adjustment is -2 (15ns), -4 (31ns) or -6 (46ns)
cycles of the internal system clock (131.072MHz).
The LOAR0 to LOAR31 registers are configured as follows:
13.5.1
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
(where n = 0 to 31)
Local Output Advancement Registers (LOAR0 to LOAR31)
Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table (continued)
Local Output Advancement Bits 1-0 (LOA1-LOA0)
LOARn Bit
BID4
1
1
1
1
1
15:2
1:0
H
to 00A2
BID3
Table 20 - Local Output Advancement (LOAR) Programming Table
1
1
1
1
1
Table 19 - Local Output Advancement Register (LOAR) Bits
H
Local Output Advancement
.
Clock Rate 131.072 MHz
BIDn
BID2
0
1
1
1
1
-2 cycles (~15ns)
-4 cycles (~31ns)
-6 cycles (~46ns)
0 (Default)
Reserved
LOA[1:0]
Name
BID1
1
0
0
1
1
Zarlink Semiconductor Inc.
ZL50062/4
BID0
1
0
1
0
1
Reset
Value
0
0
46
SMPL_MODE
Input Data
Bit Delay
Reserved
Must be set to 0 for normal operation
Local Output Advancement Value
= LOW
6 3/4
7 1/4
7 1/2
7 3/4
7
LOA1
Advancement Bits
0
0
1
1
Corresponding
Input Data
Bit Delay
Description
6
7
7
7
7
SMPL_MODE
= HIGH
LOA0
0
1
0
1
Input Data
Sampling
Point
2/4
3/4
4/4
1/4
2/4
Data Sheet