zl50064 Zarlink Semiconductor, zl50064 Datasheet - Page 22

• Manufacturer Part Number: zl50064
• Description: 16 K Channel Digital Switch With High Jitter Tolerance, Single Rate 2, 4, 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

2.3
The ZL50062 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are
aligned to the master frame pulse. The ZL50064 only generates one frame pulse output, FP8o. There is a constant
throughput delay for data being switched from the input to the output of the device such that data which is input
during Frame N is output during Frame N+2.
For further details of frame pulse conditions and options, see Section 13.1, Control Register (CR), Figure 16, Frame
Boundary Conditions, ST-BUS Operation, and Figure 17, Frame Boundary Conditions, GCI-Bus Operation.
The t
the “AC Electrical Characteristics,” on page 52. Note that although the figure above shows the traditional setups of
the frame pulses and clocks for both ST-BUS and GCI-Bus configurations, the devices can be configured to
accept/generate double-width frame pulses (if the FPW bit in the Control Register is set) as well as to use the
opposite clock edge for frame-boundary determination (using the C8IPOL and COPOL bits in the Control Register).
See the timing diagrams in “AC Electrical Characteristics,” on page 52 for all of the available configurations.
2.4
To improve the jitter tolerance of the ZL50062/64, a Frame Boundary Discriminator (FBD) circuit was added to the
device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled.
The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits
FBD_MODE[2:0] are set to 000
FBD_MODE[2:0] are set to 111
are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set
HIGH, bits FBD_MODE[2:0] should be set to 111
To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be
optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by
programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused
FBOS
Input Frame Pulse and Generated Frame Pulse Alignment
Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
BSTo/LSTo0-31
BSTo/LSTo0-31
BSTo/LSTo0-31
BSTo/LSTo0-31
BSTi/LSTi0-31
BSTi/LSTi0-31
BSTi/LSTi0-31
BSTi/LSTi0-31
is the offset between the input frame pulse, FP8i, and the generated output frame pulse, FP8o. Refer to
(16Mbps)
(16Mbps)
(4Mbps)
(8Mbps)
(2Mbps)
(2Mbps)
(4Mbps)
(8Mbps)
Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates
FP8o
FP8i
C8o
C8i
CH
CH0
0
CH
CH0
0
B
, the FBD can handle both low frequency and high frequency jitter. All other values
CH
1
CH0
CH
B
t
FBOS
1
CH0
, the FBD is set to handle lower frequency jitter only (<8kHz). When bits
CH
CH1
2
CH
CH1
2
CH
3
CH
CH0
3
CH0
CH
CH2
4
CH
CH2
4
CH
5
Zarlink Semiconductor Inc.
CH1
CH
5
CH1
CH
B
CH3
6
ZL50062/4
CH
CH3
6
to improve the high frequency jitter handling capability.
CH
7
CH
7
CH
CH4
8
22
CH
CH4
8
CH
9
CH
CH2
9
CH2
CH
CH5
10
CH
10
CH5
CH
11
CH
11
CH1
CH1
CH
CH6
12
CH
12
CH6
CH
13
CH3
CH
13
CH3
CH
CH7
14
CH
14
CH7
CH
15
CH
15
CH
16
CH
CH8
16
CH8
CH
17
CH4
CH
CH4
17
CH
18
CH
CH9
18
CH9
19
CH
CH
19
CH2
CH
20
CH2
CH
CH10
20
CH10
CH
21
CH5
CH
CH5
21
Data Sheet
CH
22
CH11
CH
22
CH11
CH
23
CH
23