zl50063 Zarlink Semiconductor, zl50063 Datasheet
zl50063
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zl50063 Summary of contents
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... Timing Unit C8i PLL V DD_PLL Figure 1 - ZL50063 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. 16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output ZL50063GAC • ...
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... I/O supply voltage • 5V tolerant inputs, outputs and I/Os Applications • Central Office Switches (Class 5) • Media Gateways • Class-independent switches • Access Concentrators • Scalable TDM-Based Architectures • Digital Loop Carriers ZL50063 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Device Overview The ZL50063 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports operate at 32.768Mbps. The ZL50063 contains two data memory blocks (Backplane and Local) to provide the following switching path configurations: • Input-to-Output Unidirectional, supporting 16K x 16K switching • ...
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... Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 13.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ZL50063 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Advancement Registers (LOAR0 to LOAR15 13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0 13.6 Backplane Output Advancement Registers (BOAR0 - BOAR15 13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0 13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.8 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ZL50063 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50063 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50063 PBGA Connections (196 PBGA, 15mm x 15mm) Pin Diagram (as viewed through top of package Figure 3 - 16,384 x 16,384 Channels (32Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4 - 8,192 x 8,192 Channels (32Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram Figure 7 - Input and Output (Generated) Frame Pulse Alignment for Different Data Rates ...
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... Table 18 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 19 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 20 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 21 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 22 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ZL50063 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... BSTi4 BSTi5 BSTi7 K BSTi6 BSTi9 BSTi13 VDD_IO L BSTi8 BSTi11 BSTi14 M BSTi10 BSTi15 D15 N BSTi12 D13 D10 P GND D9 D8 Figure 2 - ZL50063 PBGA Connections (196 PBGA, 15mm x 15mm) Pin Diagram ZL50063 A12 A13 R A11 A14 ODE ...
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... N11 C16o M9 FP16o P12 ZL50063 Description Master Clock (5V Tolerant Schmitt-Triggered Input). This pin accepts an 8.192MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register. Input data on both the Backplane and Local sides (BSTi0-15 and LSTi0-15) must be aligned to this clock and the accompanying input frame pulse, FP8i ...
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... B9 BORS G2 BSTo0-7 B3, A1, A2, C4, C5, B2, D2, C2 ZL50063 Description Backplane Serial Input Streams (5V Tolerant Inputs with Internal Pull-downs). These pins accept serial TDM data streams at a fixed data rate of 32.768Mbps (with 512 channels per stream). Backplane Serial Input Streams (5V Tolerant Inputs with Internal Pull-downs) ...
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... N7, P7, P6, N6, P5, M6, P4, N5, P3, P2, N3, N4, M5, N2, M4 A10 ZL50063 Description Backplane Serial Output Streams (5V Tolerant, Three-state Outputs with Slew-Rate Control). These pins output serial TDM data streams at a fixed data rate of 32.768Mbps (with 512 channels per stream). Refer to the descriptions of the BORS and ODE pins for control of the output HIGH or high impedance state ...
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... B10 TDo A12 TRST A14 ZL50063 Description Data Strobe (5V Tolerant Input). This active LOW input works in conjunction with CS to enable the microprocessor port read and write operations. Note that a minimum of 30ns must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access. ...
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... IC_OPEN A13, B12, C10, C12, P9, P11 IC_GND C1, C11, C13, D1, M7, M8, N8, P8 ZL50063 Description Power Supply for Periphery Circuits: +3.3V Power Supply for Core Circuits: +1.8V Power Supply for Analog PLL: +1.8V Ground. Internal Connections - OPEN. These pins must be left unconnected. Internal Connections - GND. These pins must be tied LOW. ...
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... This gives the maximum 16,384 x 16,384 channel capacity. Often a system design needs to differentiate between a Backplane and a Local side needs to put the switch in a bi-directional configuration. In this case, the ZL50063 can be used as shown in Figure 4 to give 8,192 x 8,192 channel bi-directional capacity. BSTi0-15 ...
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... Figure 3. • 16,384-channel x 16,384-channel non-blocking switching from input to output streams 1.1.2 Non-Blocking Bi-directional Configuration Another typical application is to configure the ZL50063 as a non-blocking bi-directional switch, as shown in Figure 4: • 8,192-channel x 8,192-channel non-blocking switching from Backplane input to Local output streams • ...
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... Local Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local Connection Memory. Refer to Section 8.1, Local Connection Memory, and Section 11.3, Local Connection Memory Bit Definition for more details. ZL50063 16 Zarlink Semiconductor Inc. Data Sheet ...
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... The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 6, ST-BUS and GCI-Bus Input Timing Diagram. The ZL50063 device will automatically detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame pulse ...
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... Input Frame Pulse and Generated Frame Pulse Alignment The ZL50063 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during Frame N is output during Frame N+2 ...
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... Therefore, jitter tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the carrier frequency. In the case of the ZL50063, the input clock is 8.192MHz, and the jitter associated with this clock can have the highest frequency component at 4.096MHz. ...
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... Bit Delay = 1 Ch254 BSTi/LSTi0- Bit Delay = 7 1/2 Ch254 BSTi/LSTi0-15 Bit Delay = 7 3/4 2 Please refer to Control Register (Section 13.1) for SMPL_MODE definition Figure 8 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 32Mbps ZL50063 Ch0 Bit Delay, 1/4 Ch0 ...
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... The Local and Backplane Output Advancement Registers, LOAR0 - LOAR15 and BOAR0 - BOAR15, are used to control the Local and Backplane output advancement respectively. The advancement is determined with reference to the internal system clock rate (131.072MHz). The advancement can cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7.6ns, -15ns or -23ns as shown in Figure 10. ZL50063 Ch127 Ch0 0 ...
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... The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE. RESET ODE (input pin) (input pin Table 1 - Local and Backplane Output Enable Control Priority ZL50063 Bit Advancement, 0 Ch255 Bit 0 Bit 7 Bit Advancement, -1 Ch255 Bit 0 Bit 7 Bit Advancement, -2 Ch255 Bit 0 Bit 7 Bit Advancement, -3 Bit 0 Bit 7 ...
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... Frame Frame N Serial Input Data Frame N Data Serial Output Data Frame N-2 Data Figure 11 - Data Throughput Delay with Input Ch0 Switched to Output Ch0 ZL50063 LE/BE OSB (Local / LORS/BORS (Control Backplane (input pin) Register bit) ...
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... Power-Up Sequence The recommended power-up sequence is for the V power-up of the V and V DD_PLL DD_CORE powered up simultaneously, but neither should 'lead' the V All supplies may be powered-down simultaneously. ZL50063 Frame N+1 Frame N+2 Frame N+3 Frame N+1Data Frame N+2 Data Frame N+3 Data 2 Frames + ( Frame N-1 Data Frame N Data ...
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... Figure 14. This can be achieved, for example, by synchronizing the de-assertion of the reset signal with the input frame pulse FP8i. FP8i RESET (case 1) RESET (case RESET assertion De-assertion of RESET must not fall within this window ZL50063 RESET de-assertion Figure 14 - Hardware RESET De-assertion 25 Zarlink Semiconductor Inc. Data Sheet ...
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... Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits, LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 3. ZL50063 Source Stream No. Source Channel No. ...
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... Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The memory test result is monitored through the Memory BIST Register. 10.0 JTAG Port The ZL50063 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. 10.1 Test Access Port (TAP) The Test Access Port (TAP) consists of four input pins and one output pin described as follows: • ...
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... TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when not driven from an external source. This pin MUST be pulled low for normal operation. 10.2 TAP Registers The ZL50063 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an Instruction Register and three Test Data Registers. 10.2.1 Test Instruction Register The JTAG interface contains a four-bit instruction register ...
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... Diagram for the arrival order of the bits. Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. ZL50063 Description Description Table 6 - Local Data Memory (LDM) Bits 29 Zarlink Semiconductor Inc ...
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... LORS pin. When HIGH, the channel is active. 12:9 LSAB[3:0] Source Stream Address Bits The binary value of these 4 bits represents the input stream number. Ignored when LMM is set HIGH. Table 8 - LCM Bits for Source-to-Local Switching ZL50063 Description Description 30 Zarlink Semiconductor Inc. Data Sheet ...
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... Bits BCAB[7:0] transmitted as data when BMM is set HIGH. Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits are output sequentially to the timeslot with BCAB[7] being output first. Table 9 - BCM Bits for Source-to-Backplane Switching ZL50063 Description Description 31 Zarlink Semiconductor Inc ...
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... See Table 13, Table 14, Table 15 and Table 16 for details. 11 Reserved 0 Reserved Must be set to 0 for normal operation ZL50063 Register Description , the Frame Boundary Discriminator can handle both low B , the Frame Boundary Discriminator is set to handle lower B ...
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... Local Connection Memory (LCM) for read or write operations. 01 selects Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 11 - Control Register Bits (continued) ZL50063 Description ODE Pin OSB bit BSTo0-15, LSTo0-15 ...
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... ZL50063 (a) Frame Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (c) Frame Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL ...
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... FP8i (g) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (h) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 16 - Frame Boundary Conditions, GCI-Bus Operation Zarlink Semiconductor Inc. ZL50063 Frame Boundary 35 Data Sheet ...
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... BPE 0 Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 s, upon completion of programming. Set LOW to abort the programming operation. Table 12 - Block Programming Register Bits ZL50063 Description 36 Zarlink Semiconductor Inc. Data Sheet . ...
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... Table 14 illustrates the bit delay and sampling point selection. LIDn LID4 LID3 LID2 Table 14 - Local Input Bit Delay and Sampling Point Programming Table ZL50063 1 / bit. 4 Reset Value 0 Reserved Must be set to 0 for normal operation 0 Local Input Bit Delay Register ...
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... Table 14 - Local Input Bit Delay and Sampling Point Programming Table (continued) ZL50063 SMPL_MODE = LOW Input Data Input Data LID0 Bit Delay Bit Delay 3/4 ...
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... Table 16 illustrates the bit delay and sampling point selection. BIDn BID4 BID3 BID2 Table 16 - Backplane Input Bit Delay and Sampling Point Programming Table ZL50063 1 / bit. 4 Reset Value 0 Reserved Must be set to 0 for normal operation 0 Backplane Input Bit Delay Register ...
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... Table 16 - Backplane Input Bit Delay and Sampling Point Programming Table (continued) ZL50063 SMPL_MODE = LOW Input Data Input Data BID0 Bit Delay Bit Delay 3/4 ...
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... When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Local Output Advancement Clock Rate 131.072 MHz Table 18 - Local Output Advancement (LOAR) Programming Table ZL50063 Reset Name Value Reserved ...
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... When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Backplane Output Advancement Clock Rate 131.072 MHz Table 20 - Backplane Output Advancement (BOAR) Programming Table ZL50063 Reset Name Value Reserved ...
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... Backplane Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Backplane Connection Memory BIST sequence (indicated by assertion of BISTCCB). A HIGH indicates Pass, a LOW indicates Fail. Table 21 - Memory BIST Register (MBISTR) Bits ZL50063 Description 43 Zarlink Semiconductor Inc. Data Sheet ...
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... The DIR register is configured as follows: Bit Name Reset Value 15:8 Reserved 7:4 RC[3:0] 3 Reserved 2:0 DID[2:0] Table 22 - Device Identification Register (DIR) Bits ZL50063 Description 0 Reserved Will be set normal operation 0000 Revision Control Bits 0 Reserved Will be set normal operation 011 Device ID 44 Zarlink Semiconductor Inc ...
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... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Operating Temperature 2 Positive Supply 3 Positive Supply 4 Positive Supply 5 Input Voltage 6 Input Voltage on 5V Tolerant Inputs Voltages are with respect to ground (V ) unless otherwise stated. SS ZL50063 Symbol Min V -0.5 DD_CORE V -0.5 DD_IO V -0.5 DD_PLL V -0 -0.5 I_5V ...
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... Output Low Voltage High-Impedance Leakage Output Pin Capacitance Voltages are with respect to ground (V ) unless otherwise stated. ss Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V) ZL50063 Sym Min Typ Max I 4 DD_Core I 240 290 DD_Core I 100 ...
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... FP8o Output Delay (from output frame boundary to frame pulse edge) 13 C8o Clock Period 14 C8o Clock Pulse Width High 15 C8o Clock Pulse Width Low 16 C8o Clock Rise/Fall Time ZL50063 Sym Level Units V 0.5V V 3.0V < DD_IO V 0.7V V 3.0V < V ...
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... FP16o Output Delay (from output frame boundary to frame pulse edge) 20 C16o Clock Period 21 C16o Clock Pulse Width High 22 C16o Clock Pulse Width Low 23 C16o Clock Rise/Fall Time ZL50063 Sym Min Typ t 117 122 OFPW16_122 OFPW16_61 t 58 ...
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... Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 17 - Input and Output Clock Timing Diagram for ST-BUS ZL50063 t IFPW244 t ...
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... Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 18 - Input and Output Clock Timing Diagram for GCI-Bus ZL50063 t IFPW244 t ...
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... Local and Backplane Data Timing Characteristic 1 Local/Backplane Input Data Sampling Point 2 Local/Backplane Serial Input Set-up Time 3 Local/Backplane Serial Input Hold Time 4 Output Frame Boundary Offset 5 Local/Backplane Serial Output Delay ZL50063 Sym Min Typ Max IDS32 t 2 SIS32 t 2 SIH32 ...
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... FP8i C8i CK_int * L/BSTi0- 32.768Mbps FP8o C8o CK_int * L/BSTo0-15 Bit1 Bit1 32.768Mbps Ch511 Ch511 Note *: CK_int is the internal clock signal of 131.072MHz Figure 19 - ST-BUS Local/Backplane Data Timing Diagram (32Mbps) ZL50063 t IDS32 t SIS32 t SIH32 OFBOS t SOD32 Bit7 Bit6 Bit5 Bit0 ...
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... FP8i C8i CK_int * L/BSTi0- 32.768Mbps FP8o C8o CK_int * L/BSTo0-15 Bit5 Bit6 32.768Mbps Ch511 Ch511 Note *: CK_int is the internal clock signal of 131.072MHz Figure 20 - GCI-Bus Local/Backplane Data Timing Diagram (32Mbps) ZL50063 t IDS32 t SIS32 t SIH32 OFBOS t SOD32 Bit0 Bit1 Bit2 Bit7 ...
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... Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Note 1: High Impedance is measured by pulling to the appropriate rail with CLK STo STo Figure 21 - Serial Output and External Control ODE ZL50063 Sym Min Typ Max ...
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... Input Clock Jitter Tolerance Jitter Frequency 1 1kHz 2 10kHz 3 50kHz 4 66kHz 5 83kHz 6 95kHz 7 100kHz 8 200kHz 9 300kHz 10 400kHz 11 500kHz 12 1MHz 13 2MHz 14 4MHz ZL50063 32.768Mbps Data Rate Units Jitter Tolerance 600 ns 600 ...
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... Note 2: There must be a minimum of 30ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a minimum of 30ns must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access). ZL50063 Sym Min Typ Max t 0 CSS ...
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... DS CS R/W A0-A14 D0-D15 READ D0-D15 WRITE DTA Figure 23 - Motorola Non-Multiplexed Bus Timing ZL50063 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t RDS t AKD 57 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH RDH V TT ...
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... TDi Input Set-up Time 7 TDi Input Hold Time 8 TDo Output Delay 9 TRST pulse width † Characteristics are over recommended operating conditions unless otherwise stated. TCK t TMSS TMS t TDIS TDi TDo TRST ZL50063 Sym Min t 100 TCKP t 80 TCKH t 80 TCKL t 10 TMSS t 10 ...
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... TOP VIEW NOTES:- 1. Controlling dimensions are in MM. 2. Seating plane is defined by the spherical crown of the solder balls. 3. Not to scale. 4. Ball arrangement array c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD BOTTOM VIEW SIDE VIEW Previous package codes: DIMENSION ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...