zl50063 Zarlink Semiconductor, zl50063 Datasheet - Page 16

• Manufacturer Part Number: zl50063
• Description: 16k-channel Digital Switch With High Jitter Tolerance, Single Rate 32mbps , And 32 Inputs And 32 Output
• Manufacturer: Zarlink Semiconductor

2.0
2.1
The device supports five switching configurations: (1) Unidirectional switch, (2) Backplane-to-Local, (3)
Local-to-Backplane, (4) Backplane-to-Backplane, and (5) Local-to-Local. The following sections describe the
switching paths in detail. Configurations (2) - (5) enable a non-blocking bi-directional switch with 8,192 Backplane
input/output channels at Backplane stream data rates of 32.768Mbps, and 8,192 Local input/output channels at
Local stream data rates of 32.768Mbps. The switching paths of configurations (2) to (5) may be operated
simultaneously.
2.1.1
The device can be configured as a 16,384 x 16,384 unidirectional switch by grouping together all input streams and
all output streams. All streams operate at a data rate of 32.768Mbps.
2.1.2
The device can provide data switching between the Backplane input port and the Local output port. The Local
Connection Memory determines the switching configurations.
2.1.3
The device can provide data switching between the Local input port and the Backplane output port. The Backplane
Connection Memory determines the switching configurations.
2.1.4
The device can provide data switching between the Backplane input and output ports. The Backplane Connection
Memory determines the switching configurations.
2.1.5
The device can provide data switching between the Local input and output ports. The Local Connection Memory
determines the switching configurations.
2.1.6
The Local port has 16 input (LSTi0-15) and 16 output (LSTo0-15) data streams. Similarly, the Backplane port has
16 input (BSTi0-15) and 16 output (BSTo0-15) data streams. All the streams operate at 32.768Mbps. The timing of
the input and output clocks and frame pulses is shown in Figure 7, “Input and Output (Generated) Frame Pulse
Alignment for Different Data Rates” on page 18. The input traffic are aligned based on the FP8i and C8i input timing
signals, while the output traffic are aligned based on the FP8o and C8o output timing signals.
2.1.6.1
Operation of stream data in Connection Mode or Message Mode is determined by the state of the LMM bit of the
Local Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection
Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the
Local Connection Memory. Refer to Section 8.1, Local Connection Memory, and Section 11.3, Local Connection
Memory Bit Definition for more details.
Switching Configuration
Functional Description
Unidirectional Switch
Backplane-to-Local Path
Local-to-Backplane Path
Backplane-to-Backplane Path
Local-to-Local Path
Port Operation
Local Output Port
Zarlink Semiconductor Inc.
ZL50063
16
Data Sheet