zl50063 Zarlink Semiconductor, zl50063 Datasheet - Page 29

• Manufacturer Part Number: zl50063
• Description: 16k-channel Digital Switch With High Jitter Tolerance, Single Rate 32mbps , And 32 Inputs And 32 Output
• Manufacturer: Zarlink Semiconductor

11.0
When the most significant bit, A14, of the address bus is set to ’1’, the microprocessor performs an access to one of
the device’s internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local
Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location
within the particular memory is being accessed.
The device contains two data memory blocks, one for received Backplane data and one for received Local data. For
all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored
sequentially in the relevant data memory.
11.1
The 8-bit Local Data Memory (LDM) has 8,192 positions. The locations are associated with the Local input streams
and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the addresses
of the streams and the channels. The LDM is read-only and configured as follows:
Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
Address Bit
A13-A9
A8-A0
15:8
Bit
7:0
A14
Local Data Memory Bit Definition
Memory Address Mappings
Table 5 - Address Map for Data and Connection Memory Locations (A14 = 1)
Reserved
Selects memory or register access (0 = register, 1 = memory).
Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane
Data) is accessed depends on the MS[2:0] bits in the Control Register.
Stream address (0 - 15)
Streams 0 to 15 are used
Channel address (0 - 511)
Channels 0 to 511 are used when serial stream is at 32.768Mbps
Name
LDM
Set to a default value of 8’h00.
Local Data Memory - Local Input Channel Data.
The LDM[7:0] bits contain the timeslot data from the Local side input TDM
stream. LDM[7] corresponds to the first bit received, i.e. bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 6, ST-BUS and GCI-Bus Input Timing
Diagram for the arrival order of the bits.
Table 6 - Local Data Memory (LDM) Bits
Zarlink Semiconductor Inc.
ZL50063
29
Description
Description
Data Sheet