zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 102

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

14.10.2
I
Accessed by CPU, serial interface and I
14.10.3
I
Accessed by CPU, serial interface and I
2
2
C Address F1, CPU Address:h601
C Address F2, CPU Address:h602)
Bits [3:0]:
Bits [7:4]:
Bits [0]:
Bits [1]:
Bit [2]:
Bit [3]:
MII_OP1 – MII Register Option 1
FEN – Feature Register
7
Speed bit location
7
DML
Statistic Counter Enable (Default 0)
0 – Disable
1 – Enable (all ports)
When statistic counter is enable, an interrupt control frame is generated to the
CPU, every time a counter wraps around. This feature requires an external
CPU.
Rate Control Enable (Default 0)
•
•
This bit enables/disables the rate control for all 10/100 ports. To start rate
control in a 10/100 port the rate control memory must be programmed. This
feature requires an external CPU. See Programming QoS Registers application
note and Processor Interface application note for more information.
Support DS EF Code. (Default 0)
•
•
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110
and drop is set for 0.
Enable VLAN spanning tree support (Default 0)
•
•
When VLAN spanning tree is enable the registers ECR1Pn are NOT used to
program the port spanning tree status. The port status is programmed using the
Control Command Frame.
6
Mii
0 – Disable
1 – Enable; Must also set ECR2Pn[3] = 1
0 – Disable
1 – Enable (all ports)
0 – Disable
1 – Enable
Duplex bit location in vendor specified register
Speed bit location in vendor specified register
(Default 00)
5
Rp
4
4
IP Mul
2
2
C (R/W)
C (R/W)
3
Duplex bit location
3
V-Sp
Zarlink Semiconductor Inc.
ZL50418
2
DS
102
RC
1
0
0
SC
Data Sheet