zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 148
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zl50415
Manufacturer Part Number
zl50415
Description
Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50415.pdf
(163 pages)
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15.5.5
Typical CPU Timing Diagram for a CPU Write Cycle
P_ADDR
P_CS#
P_WE#
DATA to VTX2600
DATA to ZL5041x
Write Cycle
Write Set up Time
Write Active Time
Write Hold Time
Write Recovery time
Data Set Up time
Data Hold time
Figure 19 - Typical CPU Timing Diagram for a CPU Write Cycle
Set up time
Description
T
WS
T
DS
T
T
T
T
T
T
WS
WA
WH
WR
DS
DH
Symbol
2 SCLKs
at least
Table 17 - Write Cycle
T
Zarlink Semiconductor Inc.
ADDR0
WA
DATA 0
ZL50418
T
T
148
WH
DH
(SCLK=100 Mhz)
Min.
10
20
30
10
2
2
Hold time
Recovery Time
T
WR
Max.
T
WS
T
At least 2 SCLK
At least 3 SCLK
DS
Refer to Figure 19
2 SCLKs
at least
ADDR1
T
WA
DATA 1
T
T
WH
DH
Data Sheet
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