am79q02 ETC-unknow, am79q02 Datasheet
am79q02
Manufacturer Part Number
am79q02
Description
Quad Subscriber Line Audio-processing Circuit Qslac Devices
Manufacturer
ETC-unknow
Datasheet
1.AM79Q02.pdf
(68 pages)
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Am79Q02/021/031
Quad Subscriber Line Audio-Processing Circuit
(QSLAC™) Devices
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am79Q02/021/031 Quad Subscriber Line Audio-
Processing Circuit (QSLAC) devices integrate the key
functions of analog linecards into high-performance,
very-programmable, four-channel codec-filter devices.
The QSLAC devices are based on the proven design
of Legerity’s reliable SLAC™ device families. The
advanced ar chitecture of the Q SLAC devic es
implements four independent channels and employs
digital filters to allow software control of transmission,
thus providing a cost-effective solution for the audio-
processing function of programmable linecards.
Performs the functions of four codec/filters
Software programmable:
— SLIC input impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization (frequency response)
— Digital I/O pins
— Programmable debouncing on one input
— Time slot assigner
— Programmable clock slot and PCM transmit clock
Standard microprocessor interface
A-law, µ-law, or linear coding
Single or Dual PCM ports available
— Up to 128 channels (PCLK at 8.192 MHz) per
— Optional supervision on the PCM highway
edge options
PCM port
Advanced submicron CMOS technology makes the
Am79Q02/021/031 QSLAC devices economical, with
both the functionality and the low power consumption
needed in linecard designs to maximize linecard
density at minimum cost. When used with four Legerity
SLICs, a QSLAC device provides a complete software-
configurable solution to the BORSCHT functions.
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144,
6.176, or 8.192 MHz master clock derived from
MCLK or PCLK
Built-in test modes with loopback, tone
generation, and µ P access to PCM data
Low-power, 5.0 V CMOS technology
5.0 V only operation
Mixed state (analog and digital) impedance
scaling
Performance characteristics guaranteed over a
12 dB gain range
Real Time Data register with interrupt (open
drain or TTL output)
Supports multiplexed SLIC inputs
Broadcast state
256 kHz or 293 kHz chopper clock for Legerity
SLICs with switching regulator
Maximum channel bandwidth for V.34 modems
Publication# 080147 Rev: H Amendment: /0
Issue Date: September 2001
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