am79q02 ETC-unknow, am79q02 Datasheet - Page 37

• Manufacturer Part Number: am79q02
• Description: Quad Subscriber Line Audio-processing Circuit Qslac Devices
• Manufacturer: ETC-unknow

Commands are provided to assign values to the
following global chip parameters:
Commands are provided to read values from the
following global chip status monitors:
The following description of the MPI (Microprocessor
Interface) is valid for channel 1–4. If desired, multiple
channels may be programmed simultaneously with
identical information by setting multiple Channel
Enable bits. Channel enables are contained in the
Channel Enable register and written or read using MPI
Commands 14 and 15. If multiple Channel Enable bits
are set for a read operation, only data from the first
enabled channel will be read.
The MPI physically consists of a serial data input/
output (DIO), a data clock (DCLK), and a chip select
(CS). Individual Channel Enable bits EC1, EC2, EC3,
and EC4 are stored internally in the Channel Enable
register of the QSLAC device. The serial input consists
of 8-bit commands which may be followed with
additional bytes of input data, or may be followed by
the QSLAC device sending out bytes of data. All data
input and output is MSB (D7) first and LSB (D0) last.
All data bytes are read or written one at a time, with CS
Transmit PCM Clock Edge
Interrupt Output Drive state
Chopper Clock Frequency
Select Signaling on the PCM Highway
Select Master Clock Frequency
Channel Enable register
Debounce Time for CD1
Enable E1 Output
E1 Polarity
Real Time Data register
Power Interruption Bit
Clock Failure Bit
Interrupt Mask register
Revision Code Number
SLAC Products
going High for at least a minimum off period before the
next byte is read or written. Only a single channel
should be enabled during read commands.
All commands that require additional input data to the
device must have the input data as the next N words
written into the device (for example, framed by the next
N transitions of CS). Program all unused bits as 0 to
ensure compatibility with future parts. All commands
that are followed by output data will cause the device
to output data for the next N transitions of CS going
L ow. Th e Q S L AC d ev i c e w i l l n o t a c c e p t a ny
commands until all the data has been shifted out. The
output values of unused bits are not specified.
An MPI cycle is defined by transitions of CS and
DCLK. If the CS lines are held in the High state
between accesses, the DCLK may run continuously
with no change to the internal control data. Using this
method, the same DCLK may be run to a number of
QSLAC devices and the individual CS lines will select
the appropriate device to access. Between command
s equ enc e s, D CLK c an s tay i n th e Hi gh st ate
indefinitely with no loss of internal control information
regardless of any transitions on the CS lines. Between
bytes of a multibyte read or write command sequence,
DCLK can also stay in the High state indefinitely. DCLK
can stay in the Low state indefinitely with no loss of
internal control information, provided the CS lines
remain at a High level.
If a low period of CS contains less than 8 positive
DCLK transitions, it will be ignored. If it contains 8–15
positive transitions, only the last 8 transitions matter. If
it contains 16 or more positive transitions, it will cause
a hardware reset in the part. If the chip is in the middle
of a read sequence when CS goes Low, data will be
present at the DIO pin even if DCLK has no activity.
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