am79q02 ETC-unknow, am79q02 Datasheet - Page 9

• Manufacturer Part Number: am79q02
• Description: Quad Subscriber Line Audio-processing Circuit Qslac Devices
• Manufacturer: ETC-unknow

Pin Names
DCLK
DIO
DRA/DRB
DXA/DXB
FS
INT
MCLK/E1
PCLK
RST
TSCA,
TSCB
VIN
1
–VIN
4
Input
Input/Output
Inputs
Outputs
Input
Output
Input/Output
Input
Input
Outputs
Inputs
Type
Data Clock. The Data Clock input shifts data into and out of the microprocessor interface of
the QSLAC device. The maximum clock rate is 4.096 MHz.
Data. Control data is serially written into and read out of the QSLAC device via the DIO pin,
with the most significant bit first. The Data Clock determines the data rate. DIO is high im-
pedance except when data is being transmitted from the QSLAC device.
PCM Data Receive A/B. The PCM data for channels 1, 2, 3, and 4 is serially received on either
the DRA or DRB port during user-programmed time slots. Data is always received with the
most significant bit first. For compressed signals, 1 byte of data for each channel is received
every 125 µs at the PCLK rate. In the Linear state, two consecutive bytes of data for each
channel are received every 125 µs at the PCLK rate. DRB is not available on all package types.
PCM Data Transmit. The transmit data from channels 1, 2, 3, and 4 is sent serially out on
either the DXA or DXB port or both ports during user-programmed time slots. Data is always
transmitted with the most significant bit first. The output is available every 125 µs and the
data is shifted out in 8-bit (16-bit in Linear or PCM Signaling state) bursts at the PCLK rate.
DXA and DXB are High impedance between time slots, while the device is in the Inactive
state with no PCM signaling, or while the Cutoff Transmit Path bit (CTP) is on. DXB is not
available on all package types.
Frame Sync. The Frame Sync pulse is an 8 kHz signal that identifies Time Slot 0, Clock Slot
0 of a system’s PCM frame. The QSLAC device references individual time slots with respect
to this input, which must be synchronized to PCLK.
Interrupt. INT is an active Low output signal which is programmable as either TTL compati-
ble or open drain. The
Data register changes state and is not masked. It also goes Low any time new transmit data
appears if this interrupt is armed.
the microprocessor interface, or the QSLAC device receives either a software or hardware
reset. The individual CDx
an interrupt by using Command 26 of the MPI. The transmit data interrupt must be armed
with a bit in the Operating Conditions register.
Master Clock (Input)/Enable CD1 Multiplex (Output). The Master Clock can be a 1.536 MHz,
1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor. If the
internal clock is derived from the PCM Clock Input (PCLK), this pin can be used as an E1 out-
put to control Legerity SLICs having multiplexed hookswitch and ground-key detector out-
puts.
PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or
out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maxi-
mum clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for dual
PCM highway versions and 256 kHz for single PCM highway versions. The minimum clock
rate must be doubled if Linear state or PCM signaling is used. PCLK frequencies between
1.03 MHz and 1.53 MHz are not allowed. Optionally, the digital signal processor clock can
be derived from PCLK rather than MCLK.
Reset. A logic Low signal at this pin resets the QSLAC device to its default state. The RST
pin may be tied to VCCD if it is not needed in the system.
Time Slot Control. The Time Slot Control outputs are open drain outputs (requiring pull-up
resistors to VCCD) and are normally inactive (High impedance).
(Low) when PCM data is transmitted on the DXA or DXB pin respectively.
Analog. The analog voice band signal is applied to the VIN input of the QSLAC device. The
VIN input is biased at VREF by a large internal resistor. The audio signal is sampled, digitally
processed and encoded, and then made available at the TTL-compatible PCM output (DXA
or DXB). If the digitizer saturates in the positive or negative direction, VIN is pulled by a re-
duced resistance toward AGND or VCCD, respectively. VIN
is the input for channel 2, VIN
SLAC Products
INT
y
bits in the Real Time Data register can be masked from causing
output goes Low any time one of the input bits in the Real Time
3
is the input for channel 3, and VIN
INT
remains Low until the appropriate register is read via
Description
1
is the input for channel 1, VIN
TSCA
4
is the input for channel 4.
or
TSCB
is active
2
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