am79q02 ETC-unknow, am79q02 Datasheet - Page 21

• Manufacturer Part Number: am79q02
• Description: Quad Subscriber Line Audio-processing Circuit Qslac Devices
• Manufacturer: ETC-unknow

Master Clock
Auxiliary Output Clocks
Notes:
1. If CFAIL = 1 (Command 23), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating
2. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
3. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock
4. TSC is delayed from FS by a typical value of N • t
5. t
6. There is a special conflict detection circuitry that will prevent high-power dissipation from occurring when the DXA or DXB
SWITCHING WAVEFORMS
Input and Output Waveforms for AC Tests
Master Clock Timing
No.
No.
all channels or switching them to default coefficients; otherwise, a chip select off time of 25 µs is required. If the low power
state (LPM = 1, Command 14) is selected and MCLK is also lost, this minimum chip select off time increases to 75 µs.
frequency is 8.192 MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The
minimum clock frequency is 128 kHz in Companded state and 256 kHz in Linear state, PCM Signaling state. The minimum
PCM clock rates should be doubled for parts with only one PCM highway in order to allow simultaneous access to all four
channels.
pins of two QSLAC devices are tied together and one QSLAC device starts to transmit before the other has gone into a
High-impedance state.
TSO
37
38
39
40
41
42
43
44
is defined as the time at which the output achieves the Open Circuit state.
Symbol
Symbol
A
t
t
t
t
f
MCR
MCH
MCF
MCL
CHP
f
t
MCY
E1
E1
Master clock accuracy
Rise time of clock
Fall time of clock
MCLK High pulse width
MCLK Low pulse width
Chopper clock frequency
E1 output frequency (CMODE = EE1 = 1)
E1 pulse width (CMODE = EE1 = 1)
0.45
2.4
V
Parameter
IL
40
Parameter
V
IH
39
41
PCY
2.0
0.8
SLAC Products
, where N is the value stored in the time/clock-slot register.
CHP = 0
CHP = 1
37
Points
Test
Min
–100
48
48
Min
0.8
2.0
Typ
38
292.57
4.923
31.25
Typ
256
Max
+100
Max
15
15
Units
kHz
Units
µs
ppM
ns
19256A-015
19256A-016
Note
Note
21