am79q02 ETC-unknow, am79q02 Datasheet - Page 26

• Manufacturer Part Number: am79q02
• Description: Quad Subscriber Line Audio-processing Circuit Qslac Devices
• Manufacturer: ETC-unknow

.
E1 Multiplex Operation
The QSLAC device can multiplex input data from the
CD1 SLIC I/O pin into two separate status bits per
channel (CD1 and CD1B bits in the SLIC Input/Output
register, Commands 52/53h, and CDA and CDB bits in
the Real Time Data register, Commands 4D/4Fh)
using the E1 multiplex mode. This multiplex mode
provides the means to accommodate dual detect
states when connected to an Legerity SLIC device,
which also supports ground-key detection in addition
to loop detect. Legerity SLICs that support ground-key
detect use their E1 pin as an input to switch the SLIC’s
single detector (DET) output between internal loop
detect or ground-key detect comparators. Using the E1
multiplex mode, a single QSLAC device can monitor
both loop detect and ground-key detect states of all
four connected SLICs without additional hardware.
Although normally used for ground key detect, this
multiplex function can also be used for monitoring
other signal states.
The E1 multiplex mode is selected by setting the EE1
bit (bit 7, Command C8/C9h) and CMODE bit (bit 4,
Command 46/47h) in the QSLAC device. The CMODE
bit must be selected (CMODE=1) for the master clock
to be derived from PCLK so that the MCLK/E1 pin can
be used as an output for the E1 signal. The multiplex
mode is then turned on by setting the EE1 bit. With the
26
Assigner
Engine
Time
Pulses
Slot
DSP
E1P
Notes:
1. CMODE = Command 12, 13
2. CSEL = Command 12, 13
3. EE1 = Command 45, 46
4. E1P = Command 45, 46
E1
Am79Q02/021/031 Data Sheet
Figure 8. Clock Mode Option
CMODE
÷
N
(= 1)
E1 multiplex mode enabled, the QSLAC device
generates the E1 output signal. This signal is a
31.25 µ s (1/32 kHz) duration pulse occurring at a
4.923 kHz (64 kHz/13) rate. The polarity of this E1
output is selected by the E1P bit (bit 6, Command C8/
C9h) allowing this multiplex mode to accommodate all
SLICs regardless of their E1 high/low logic definition.
Figure 9 shows the SLIC Input/Output register, I/O
pins, E1 multiplex hardware operation for one QSLAC
device channel. It also shows the operation of the Real
Time Register. The QSLAC device E1 output signal
connects directly to the E1 inputs of all four connected
SLICs and is used by those SLICs to select an internal
comparator to route to the SLIC’s DET output. This E1
signal is also used internally by the QSLAC device for
controlling the multiplex operation and timing.
The CD1 and CD1B bits of the SLIC Input/Output
register are isolated from the CD1 pin by transparent
latches. When the E1 pulse is off, the CD1 pin data is
routed directly to the CD1 bit of the SLIC I/O register
and changes to the CD1B bit of that register are
disabled by its own latch. When E1 pulses on, the CD1
latch holds the last CD1 state in its register. At the
same time, the CD1B latch is enabled, which allows
CD1 pin data to be routed directly to the CD1B bit.
CSEL
PCLK
(= 0)
(= 0)
Bit 4
Bits 0–3
Bit 7
Bit 6
MCLK/E1
(= 1)
(= 1)
(= 0)
EE1
E1