oq2541bhp NXP Semiconductors, oq2541bhp Datasheet - Page 9

• Manufacturer Part Number: oq2541bhp
• Description: Oq2541bhp; Oq2541bu Sdh/sonet Data And Clock Recovery Unit Stm1/4/16 Oc3/12/48 Ge
• Manufacturer: NXP Semiconductors

Philips Semiconductors
External capacitor for loop filter
The loop filter is an integrator with a built-in capacitance of
2
window detector is active, an external capacitance of
360 nF (2 times 180 nF parallel) must be connected
between pins CAPUPQ and CAPDOQ.
Loop mode enable
The loop mode is provided for system testing (see Fig.8).
The loop mode is enabled by applying a voltage between
the loop mode: the outputs on pins DLOOP, DLOOPQ,
CLOOP and CLOOPQ are switched on.
If a voltage higher than 2.0 V (HIGH-level TTL) or lower
than 2.0 V is applied to pin ENL, then pins DOUT,
DOUTQ, COUT and COUTQ are switched on while
pins DLOOP, DLOOPQ, CLOOP and CLOOPQ are
disabled to minimize power consumption.
All outputs active
All outputs (normal outputs DOUT, DOUTQ, COUT,
COUTQ and loop mode outputs DLOOP, DLOOPQ,
CLOOP and CLOOPQ) can be activated by applying a
voltage lower than 2.0 V or higher than +2.0 V to
pin ALLON. If the voltage on this pin is between
pin ENL. The input has the same structure as the
ENL input (see Fig.8).
2000 Sep 18
handbook, halfpage
0.8 and +0.8 V (LOW-level TTL) to pin ENL. This selects
0.8 and +0.8 V, the active outputs can be selected by
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
Fig.8
130 pF. To ensure loop stability while the frequency
BYPASS
ALLON,
off chip
ENL,
V EE
Input circuit of pins ENL, ALLON and
BYPASS.
GND
on chip
36 k
DECODER
LOGIC
MGT206
9
Bypass mode
The bypass mode is provided to use the OQ2541B at non
standard SDH/SONET or GE bit rates. The data recovery
and clock extraction function can be bypassed if no clock
extraction is needed, or when the bit rate is different from
155, 622, 1250 or 2488 Mbit/s. Here, the incoming data
from DIN and DINQ is directly fed to the RF outputs. Clock
outputs COUT, COUTQ, CLOOP, CLOOPQ and the
LOS detection have no meaning in this mode.
In the bypass mode, the data and clock recovery circuit is
disabled to reduce crosstalk. The bypass mode can be
activated by applying a voltage lower than 2.0 V or higher
than +2.0 V to pin BYPASS. If the voltage on this pin is
between 0.8 and +0.8 V, extracted data and recovered
clock are present on the RF outputs (normal
DCR operation). The input has the same structure as the
ENL input (see Fig.8).
Lock detection
Pin LOCK should be interpreted as an indication of the
presence of the reference clock on pin CREF and of the
proper functioning of the acquisition aid (frequency
window detector).
Pin LOCK is an open-collector TTL output and is to be
pulled up with a 10 k resistor to a positive supply voltage.
If the VCO frequency is within a 1000 ppm window around
the desired frequency, pin LOCK will stay at a HIGH level.
If no reference clock is present, or the VCO is outside the
1000 ppm window, pin LOCK will be at a LOW level. The
logic level on pin LOCK does not indicate locking of the
PLL to the incoming data; this is indicated by the signal on
pin LOS.
Loss of signal detection
The LOS function is closely related to the functionality of
the Alexander phase detector; see Fig.3 for the meaning
of A, B and T in this section.
The functional description states that the phase detector
does not take any action if the value at sample points
A and B are the same, as there has not been any
transition. However, if levels A and B are the same but
different from level T, this still means there has not been
any transition, but level T has got the wrong level
somehow. This is probably due to noise or bad signal
integrity, which will lead to a bit error. Hence, the
occurrence of this particular situation is an indication of bit
errors. If too many of these bit errors occur per time and
the PLL is gradually losing lock, the LOS alarm is asserted.
The LOS alarm assert level is around BER = 5
the de-assert level is around BER = 1
OQ2541BHP; OQ2541BU
Product specification
10
3
.
10
2
and