am49pdl127ah Meet Spansion Inc., am49pdl127ah Datasheet
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Am49PDL129AH Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
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... ADVANCE INFORMATION Am49PDL127AH/Am49PDL129AH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit ( 16-Bit) CMOS Pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — Access time as fast initial / 25 ns page Package — ...
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... Deep power-down standby: 5 µA CE1s# and CE2ps Chip Select Power down features using CE1s# and CE2ps Data retention supply voltage: 2.7 to 3.3 volt Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) 8-word page mode access Am49PDL127AH/Am49PDL129AH December 18, 2003 ...
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... AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am49PDL127AH/Am49PDL129AH de ...
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... AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am49PDL127AH/Am49PDL129AH de- CC December 18, 2003 ...
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... Table 18. Write Operation Status ................................................... 54 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 55 Figure 8. Maximum Negative Overshoot Waveform ...................... 55 Figure 9. Maximum Positive Overshoot Waveform........................ 55 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 56 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 10. Test Setup, VIO = 2.7 – 3.3 V...................................... 58 Figure 11. Input Waveforms and Measurement Levels ................. 58 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 59 CE#1ps Timing ....................................................................... 59 Figure 12. Timing Diagram for Alternating Am49PDL127AH/Am49PDL129AH 5 ...
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... Figure 29. Pseudo SRAM Write Cycle—CE1#s Control ................ 75 Figure 30. Pseudo SRAM Write Cycle— UB#s and LB#s Control.................................................................. 76 Erase And Programming Performance . . . . . . . 77 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 77 Package Pin Capacitance Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 77 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 78 TLA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 78 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 79 Am49PDL127AH/Am49PDL129AH December 18, 2003 ...
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... CE2ps December 18, 2003 Am29PDL127AH/Am49PDL129AH Flash Memory RY/BY# 128 MBit Flash Memory DQ15 to DQ0 MBit DQ15 to DQ0 Pseudo SRAM Am49PDL127AH/Am49PDL129AH Pseudo SRAM – – DQ15 to DQ0 7 ...
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... DQ15 DQ12 DQ7 DQ11 NC DQ5 DQ14 exposed to temperatures above 150°C for prolonged periods of time. Am49PDL127AH/Am49PDL129AH A10 NC Pseudo B10 SRAM Only NC Flash Only Shared F10 NC G10 NC SS L10 NC M10 NC December 18, 2003 ...
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... DQ12 DQ7 DQ11 NC DQ5 DQ14 integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am49PDL127AH/Am49PDL129AH A10 NC Pseudo B10 SRAM Only NC Flash Only D9 Shared A15 E9 A21 F9 F10 A22 NC G9 G10 A16 ...
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... RFU’s , and not connect them to any other signal. In case of any further inquiries about the above look- ahead pinout, please refer to the application note on this subject, or contact the appropriate AMD or Fujitsu sales office. Am49PDL127AH/Am49PDL129AH A10 NC B10 NC Pseudo ...
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... WE# WP#/ACC RESET# UB#s LB#s , the highest IL , these sector IH Am49PDL127AH/Am49PDL129AH PPB is programmed. When WP/ ACC#= 12V, program and erase op- erations are accelerated. = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) = pSRAM Power Supply = Device Ground (Common) ...
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... The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting M49000002I output. The following subsections describe each of M49000002J these operations in further detail. M4900000K M4900000L Am49PDL127AH/Am49PDL129AH ° C) December 18, 2003 ...
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... Standard microprocessor read cycles that assert valid all sectors will HH, addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Am49PDL127AH/Am49PDL129AH UB#s WP#/ DQ7– (Note RESET# ACC ...
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... The “Command 1 0 Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase op eration the DC Characteristics table represents the ac- CC2 tive current specification for the write mode. The Flash Am49PDL127AH/Am49PDL129AH CE#f1 CE#f2 A21–A20 0 1 00, 01 ...
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... Refer to the pSRAM AC Characteristics tables for RE- SET# parameters and to Figure 15 for the timing dia- gram. Output Disable Mode When the OE# input disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state Am49PDL127AH/Am49PDL129AH ACC before the device reduces IH CC5 , the RP ± ...
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... Am29PDL129H Table 6. Am29PDL127H Sector Architecture Bank Sector Factory-Locked Area Address Range Customer-Lockable Area 000000h–00007Fh Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127AH/Am49PDL129AH Sector Size Address Range 64 words 000000h-00003Fh 64 words 000040h-00007Fh Address Range (x16) December 18, 2003 ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127AH/Am49PDL129AH 4 000000h–000FFFh 4 001000h–001FFFh 4 002000h–002FFFh 4 003000h–003FFFh 4 004000h–004FFFh 4 005000h–005FFFh 4 006000h–006FFFh 4 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127AH/Am49PDL129AH 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127AH/Am49PDL129AH 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127AH/Am49PDL129AH 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127AH/Am49PDL129AH 4C0000h–4C7FFFh 4C8000h–4CFFFFh 4D0000h–4D7FFFh 4D8000h–4DFFFFh 4E0000h–4E7FFFh 4E8000h–4EFFFFh 4F0000h–4F7FFFh 4F8000h–4FFFFFh 500000h–507FFFh 508000h–50FFFFh 510000h–517FFFh 518000h–51FFFFh 520000h–527FFFh 528000h–52FFFFh 530000h– ...
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... Sector Address (A22-A12) Sector Size (Kwords) Am49PDL127AH/Am49PDL129AH 600000h–607FFFh 608000h–60FFFFh 610000h–617FFFh 618000h–61FFFFh 620000h–627FFFh 628000h–62FFFFh 630000h–637FFFh 638000h–63FFFFh 640000h–647FFFh 648000h–64FFFFh 650000h–657FFFh 658000h–65FFFFh 660000h–667FFFh 668000h–66FFFFh 670000h– ...
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... Am49PDL127AH/Am49PDL129AH 700000h–707FFFh 708000h–70FFFFh 710000h–717FFFh 718000h–71FFFFh 720000h–727FFFh 728000h–72FFFFh 730000h–737FFFh 738000h–73FFFFh 740000h–747FFFh 748000h–74FFFFh 750000h–757FFFh 758000h–75FFFFh 760000h–767FFFh 768000h–76FFFFh 770000h–777FFFh 778000h– ...
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... Am49PDL127AH/Am49PDL129AH Sector Size Address Range (x16) (Kwords) 32 000000h–007FFFh 32 008000h–00FFFFh 32 010000h–017FFFh 32 018000h–01FFFFh 32 020000h–027FFFh 32 028000h–02FFFFh 32 030000h–037FFFh 32 038000h–03FFFFh 32 040000h–047FFFh 32 048000h–04FFFFh 32 050000h–057FFFh 32 058000h– ...
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... Table 7. Am29PDL129H Sector Architecture (Continued) Bank Sector CE#f1 December 18, 2003 Sector Address CE#f2 (A21-A12) Am49PDL127AH/Am49PDL129AH Sector Size Address Range (x16) (Kwords) 25 ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127AH/Am49PDL129AH 32 130000h–137FFFh 32 138000h–13FFFFh 32 140000h–147FFFh 32 148000h–14FFFFh 32 150000h–157FFFh 32 158000h–15FFFFh 32 160000h–167FFFh 32 168000h–16FFFFh 32 170000h–177FFFh 32 178000h–17FFFFh 32 180000h–187FFFh 32 188000h–18FFFFh 32 190000h–197FFFh 32 198000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127AH/Am49PDL129AH 32 270000h–277FFFh 32 278000h–27FFFFh 32 280000h–287FFFh 32 288000h–28FFFFh 32 290000h–297FFFh 32 298000h–29FFFFh 32 2A0000h–2A7FFFh 32 2A8000h–2AFFFFh 32 2B0000h–2B7FFFh 32 2B8000h–2BFFFFh 32 2C0000h–2C7FFFh 32 2C8000h–2CFFFFh 32 2D0000h–2D7FFFh 32 2D8000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127AH/Am49PDL129AH 32 300000h–307FFFh 32 308000h–30FFFFh 32 310000h–317FFFh 32 318000h–31FFFFh 32 320000h–327FFFh 32 328000h–32FFFFh 32 330000h–337FFFh 32 338000h–33FFFFh 32 340000h–347FFFh 32 348000h–34FFFFh 32 350000h–357FFFh 32 358000h–35FFFFh 32 360000h–367FFFh 32 368000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127AH/Am49PDL129AH 4 000000h–000FFFh 4 001000h–001FFFh 4 002000h–002FFFh 4 003000h–003FFFh 4 004000h–004FFFh 4 005000h–005FFFh 4 006000h–006FFFh 4 007000h–007FFFh 32 008000h–00FFFFh 32 010000h–017FFFh 32 018000h–01FFFFh 32 020000h–027FFFh 32 028000h–02FFFFh 32 030000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127AH/Am49PDL129AH 32 100000h–107FFFh 32 108000h–10FFFFh 32 110000h–117FFFh 32 118000h–11FFFFh 32 120000h–127FFFh 32 128000h–12FFFFh 32 130000h–137FFFh 32 138000h–13FFFFh 32 140000h–147FFFh 32 148000h–14FFFFh 32 150000h–157FFFh 32 158000h–15FFFFh 32 160000h–167FFFh 32 168000h– ...
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... Sector Address CE#f2 (A21-A12) Am49PDL127AH/Am49PDL129AH 32 240000h–247FFFh 32 248000h–24FFFFh 32 250000h–257FFFh 32 258000h–25FFFFh 32 260000h–267FFFh 32 268000h–26FFFFh 32 270000h–277FFFh 32 278000h–27FFFFh 32 280000h–287FFFh 32 288000h–28FFFFh 32 290000h–297FFFh 32 298000h–29FFFFh 32 2A0000h–2A7FFFh 32 2A8000h– ...
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... SA175-SA178 128 (4x32) Kwords SA179-SA182 128 (4x32) Kwords SA183-SA186 128 (4x32) Kwords 128 (4x32) Kwords SA187-SA190 SA191-SA194 128 (4x32) Kwords SA195-SA198 128 (4x32) Kwords 128 (4x32) Kwords SA199-SA202 Am49PDL127AH/Am49PDL129AH 32 380000h–387FFFh 32 388000h–38FFFFh 32 390000h–397FFFh 32 398000h–39FFFFh 32 3A0000h–3A7FFFh 32 3A8000h–3AFFFFh 32 3B0000h– ...
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... Kwords SA2-63 - SA2-66 128 (4x32) Kwords SA2-67 - SA2-70 128 (4x32) Kwords SA2-71 - SA2-74 128 (4x32) Kwords SA2-75 - SA2-78 128 (4x32) Kwords SA2-79 - SA2-82 Am49PDL127AH/Am49PDL129AH 10111XXXXX 128 (4x32) Kwords 11000XXXXX 128 (4x32) Kwords 11001XXXXX 128 (4x32) Kwords 11010XXXXX 128 (4x32) Kwords 11011XXXXX ...
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... When cleared (“0”), the PPBs are change- able. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Am49PDL127AH/Am49PDL129AH 11011XXXXX 128 (4x32) Kwords 11100XXXXX 128 (4x32) Kwords ...
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... An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sec- tor. Am49PDL127AH/Am49PDL129AH . IL PPB Lock Sector State Unprotected— ...
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... PDL 129 were last set to be protected or unprotected. That is, sector protection or unprotection for these sec- tors depends on whether they were last protected or unprotected using the method described in High Volt- age Sector Protection. Am49PDL127AH/Am49PDL129AH on the WP#/ACC pin, the de the WP#/ACC pin, the de- IH ...
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... The proce- dure requires high voltage (V RESET# pin. Refer to Figure 1 for details on this pro- cedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. Am49PDL127AH/Am49PDL129AH ) to be placed on the ID 37 ...
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... PLSCNT = 1000? Yes Remove V from RESET# Write reset command Sector Unprotect complete Device failed Sector Unprotect Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms Am49PDL127AH/Am49PDL129AH START PLSCNT = 1 RESET Wait 4 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors ...
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... The Customer-lockable SecSi Sector area can be pro- tected using one of the following procedures: Follow the SecSi Sector Protection Algorithm as shown in Figure 3. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only appli- cable to the SecSi Sector. Am49PDL127AH/Am49PDL129AH 39 ...
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... A7–A0 = 00011010 Read from sector address with A7–A0 = 00011010 No Data = 01h? Yes SecSi Sector Protection Completed SecSi Sector Exit Write 555h/AAh Write 2AAh/55h Write SA0+555h/90h Write XXXh/00h Am49PDL127AH/Am49PDL129AH SecSi Sector Entry SecSi Sector Protection SecSi Sector Exit December 18, 2003 ...
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... CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alterna- tively, contact an AMD representative for copies of these documents initiate a IH Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Am49PDL127AH/Am49PDL129AH and OE during power up ...
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... CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Am49PDL127AH/Am49PDL129AH N µs N µ s (00h = not supported) N ...
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... Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported Supported Bank Organization 00 = Data at 4Ah is zero Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 Am49PDL127AH/Am49PDL129AH 43 ...
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... The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Am49PDL127AH/Am49PDL129AH Table 4 shows the address range December 18, 2003 ...
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... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the table in the AC Characteristics section for parameters, and Figures 16 Am49PDL127AH/Am49PDL129AH any operation HH Erase and Program Operations and 17 for timing diagrams. 45 ...
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... When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- Am49PDL127AH/Am49PDL129AH December 18, 2003 ...
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... The actual password is 64- bits long. Four Password Program commands are re- quired to program the password. The system must enter the unlock cycle, password program command (38h) and the program address/data for each portion Am49PDL127AH/Am49PDL129AH Autoselect Command Sequence sections 47 ...
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... The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hard- ware reset. Exiting the DYB Write command is accom- plished by writing the Read/Reset command. Am49PDL127AH/Am49PDL129AH -level SecSi Sector CC December 18, 2003 ...
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... Sector Protection Status Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sec- tor Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group. Am49PDL127AH/Am49PDL129AH 49 ...
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... Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array. Am49PDL127AH/Am49PDL129AH Data Addr Data Addr 01 7E ...
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... Following the final cycle of the command sequence, the user must write the first three cycles of the Autoselect command and then write a Reset command. 18. If checking the DYB status of sectors in multiple banks, the user must follow Note 17 before crossing a bank boundary. Am49PDL127AH/Am49PDL129AH Data Addr Data Addr ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm Am49PDL127AH/Am49PDL129AH Figure 6 START Addr = VA Yes No ...
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... Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 7. Toggle Bit Algorithm Am49PDL127AH/Am49PDL129AH Figure 21 section shows the tog- START Read Byte (DQ7– ...
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... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits. Am49PDL127AH/Am49PDL129AH December 18, 2003 ...
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... The device outputs array data if the system addresses a non-busy bank. December 18, 2003 Table 18. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am49PDL127AH/Am49PDL129AH DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...
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... Operating ranges define those limits between which the functionality of the device is guaranteed +0.8 V –0.5 V –2 Figure 8. Maximum Negative +0 +2 +0.5 V 2.0 V Figure 9. Maximum Positive Am49PDL127AH/Am49PDL129AH Overshoot Waveform Overshoot Waveform December 18, 2003 ...
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... Embedded Erase or Embedded Program progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for t current is 1 µ CCmax 6. Not 100% tested. Am49PDL127AH/Am49PDL129AH Min Typ Max Unit ±1.0 µA 35 µA 35 µA ±1.0 µA ...
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... Max Chip Enabled OUT t = Min –2 0 Chip Disabled t = 85C 3 Am49PDL127AH/Am49PDL129AH Min Typ Max Unit 0.5 µA 0.5 µ 0 – 0.2 80 µA –0.3 0 2.2 V 0.3 December 18, 2003 ...
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... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels = 2.7 – 3.3 V INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am49PDL127AH/Am49PDL129AH 66, 70 Unit 1 TTL gate 0.0–3 ...
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... JEDEC Std Description — t CE#1ps Recover Time CCR CE#f CE1#s CE2s Figure 12. Timing Diagram for Alternating — t CCR t CCR Between Pseudo SRAM and Flash Am49PDL127AH/Am49PDL129AH Test Setup All Speeds Unit Min CCR t CCR December 18, 2003 ...
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... CE#f1 Read Toggle and Data# Polling 5. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V bus driven CE#f2 Valid CE#f1/CE#f2 transitions: (CE#f1= V (CE#f1 (CE#f1 Am49PDL127AH/Am49PDL129AH Speed Options 66 70 Min 65 70 Max Max Max 25 30 Max ...
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... Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 13. Read Operation Timings Same Page PACC t ACC Qa ; During CE#f2 transitions, CE#f1 Am49PDL127AH/Am49PDL129AH HIGH PACC PACC December 18, 2003 ...
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... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 15. Reset Timings Am49PDL127AH/Am49PDL129AH All Speed Options Unit µs 20 500 ns 500 µ ...
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... Write Recovery Time from RY/BY Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information Word Am49PDL127AH/Am49PDL129AH Speed 66 70 Unit Min Min 0 ns Min ...
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... WPH A0h t BUSY is the true data at the program address. OUT IH. Figure 16. Program Operation Timings Am49PDL127AH/Am49PDL129AH Read Status Data (last two cycles WHWH1 Status D OUT VHH 65 ...
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... For PDL129 during CE#f1 transitions the other CE#f1 pin = V Figure 18. Chip/Sector Erase Operation Timings SADD 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY . IH Am49PDL127AH/Am49PDL129AH Read Status Data WHWH2 In Complete Progress t RB December 18, 2003 ...
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... OH DH Valid Valid In Out t SR/W Read Cycle ACC Complement Complement Status Data Status Data Am49PDL127AH/Am49PDL129AH Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data 67 ...
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... AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 22. DQ2 vs. DQ6 Am49PDL127AH/Am49PDL129AH Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read December 18, 2003 ...
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... VIDR CE#f1 or CE#f2 (PDL129 only) WE# RY/BY# Figure 23. Temporary Sector Unprotect Timing Diagram December 18, 2003 Min Min Min Min Program or Erase Command Sequence t RSP Am49PDL127AH/Am49PDL129AH All Speed Options Unit 500 ns 250 ns µs 4 µ ...
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... For PDL129 during CE#f1 transitions the other CE#f1 pin = V Figure 24. Sector/Sector Block Protect and Valid* 60h 60h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Unprotect Timing Diagram Am49PDL127AH/Am49PDL129AH Valid* Valid* Verify 40h Status December 18, 2003 ...
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... Word or Byte (Note Sector Erase Operation (Note 2) WHWH2 WHWH2 Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. December 18, 2003 Word Am49PDL127AH/Am49PDL129AH Speed 66 70 Unit Min Min 0 ns ...
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... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am49PDL127AH/Am49PDL129AH PA DQ7# D OUT December 18, 2003 ...
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... CE# Min Max Max Max Max Min Min Min Max Max Max Min UB#s and/or LB for continuous periods < 10 µs. RC Am49PDL127AH/Am49PDL129AH . IH Speed Unit ...
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... CO1 t CO2 OLZ t BLZ t LZ (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ for continuous periods < 10 µs. RC Figure 27. Pseudo SRAM Read Cycle Am49PDL127AH/Am49PDL129AH OHZ Data Valid December 18, 2003 ...
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... Note (See Note (See Note 3) High-Z t WHZ Data Undefined applied in case a write ends as CE1#s or WE# going high low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low Am49PDL127AH/Am49PDL129AH Speed Unit ...
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... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low Am49PDL127AH/Am49PDL129AH t (See Note Data Valid High-Z is measured from the beginning of ...
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... WP (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low Figure 30. Pseudo SRAM Write Cycle— UB#s and LB#s Control Am49PDL127AH/Am49PDL129AH t (See Note Data Valid ...
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... V, 1,000,000 cycles. All values are subject to change. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT Test Conditions Am49PDL127AH/Am49PDL129AH Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec Excludes system level µs overhead (Note 5) µs sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... IN THE OUTER ROW E/2 BALL PITCH 8. "+" INDICATES THE THEORETICAL CENTER OF SOLDER BALL PLACEMENT DEPOPULATED BALLS. DEPOPULATED SOLDER BALLS 9. NOT USED. 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Am49PDL127AH/Am49PDL129AH ...
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... AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies 2 Am49PDL127AH/Am49PDL129AH December 18, 2003 ...