am49pdl127ah Meet Spansion Inc., am49pdl127ah Datasheet - Page 15

• Manufacturer Part Number: am49pdl127ah
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 16 Mbit 1m ? 16-bit Cmos Pseudo Static Ram
• Manufacturer: Meet Spansion Inc.

Operation
(Notes 1, 2)
Read from
Active Flash
Write to Active
Flash
Standby
Deep Power-down
Standby
Output Disable (Note 9)
Flash Hardware
Reset
Sector Protect
(Notes 6, 10)
Sector
Unprotect
(Notes 5, 9)
Temporary
Sector
Unprotect
Read from pSRAM
Write to pSRAM
Legend: L = Logic Low = V
Address In, D
Notes:
1.
2. Do not apply CE#f1 or 2 = V
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
5. The sector protect and sector unprotect functions may also be
6. If WP#/ACC = V
7. Data will be retained in pSRAM.
8. Data will be lost in pSRAM.
9.
December 18, 2003
Other operations except for those indicated in this column are
inhibited.
the same time.
= V
If WP#/ACC = V
40%.
implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
protected. If WP#/ACC = V
protection depends on whether they were last protected or
unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = V
be unprotected.
Both CE#f1 inputs may be held low for this operation.
IH
the boot sectors protection will be removed.
IN
= Data In, D
(Note 7)
(Note 8)
(Note 7)
(Note 8)
(Note 7)
(Note 8)
(Note 7)
(Note 9)
(Note 7)
(Note 8)
(Note 7)
(Note 8)
IL
ACC
IL
, the boot sectors will be protected. If WP#/ACC
, the two outermost boot sectors remain
(9V), the program time will be reduced by
Active
CE#f1
IL
L (H)
L (H)
L (H)
L (H)
L (H)
OUT
, H = Logic High = V
H
H
V
V
IH
IL
CC
CC
= Data Out
, the two outermost boot sector
, CE#1ps = V
± 0.3 V
± 0.3 V
X
X
(PDL129
CE#f2
only)
H (L)
H (L)
H (L)
H (L)
H (L)
H
H
A D V A N C E
IL
CE#1ps CE2ps OE# WE#
IH
and CE2ps = V
Am49PDL127AH/Am49PDL129AH
Table 1. Device Bus Operations
HH,
, V
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
ID
all sectors will
= 11.5–12.5 V, V
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
IH
at
I N F O R M A T I O N
H
X
X
H
H
X
H
H
X
X
L
L
HH
H
H
H
H
X
X
X
X
L
L
L
L
= 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, A
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the OE# and appropriate CE#f1/CE#f2 (PDL129
only) pins to V
trol and for PDL129 select the lower (CE#f1) or upper
(CE#f2) halves of the device. OE# is the output control
and gates array data to the output pins. WE# should
remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
A1 = H,
A6 = H,
A1 = H,
A6 = L,
SADD,
A0 = L
SADD,
A0 = L
Addr.
A
A
A
A
X
X
X
X
X
X
IN
IN
IN
IN
(Note
IH
LB#s
3)
X
X
X
X
X
X
X
X
X
X
H
H
L
L
L
L
.
IL
. CE#f1 and CE#f2 are the power con-
UB#s
(Note
3)
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
RESET#
V
V
0.3 V
0.3 V
V
V
V
CC
CC
H
H
H
H
H
L
ID
ID
ID
±
±
(Note 4)
(Note 4)
(Note 6)
(Note 6)
WP#/
ACC
L/H
L/H
L/H
L/H
H
H
X
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z
High-Z
DQ7–
D
D
D
DQ0
D
D
D
D
D
D
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
DQ15–
High-Z
High-Z
High-Z
IN
D
D
D
DQ8
D
D
D
OUT
OUT
OUT
X
X
=
IN
IN
IN
13