lrs1386 Sharp Microelectronics of the Americas, lrs1386 Datasheet - Page 36
![no-image](/images/no-image-200.jpg)
lrs1386
Manufacturer Part Number
lrs1386
Description
Flash Memory
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LRS1386.pdf
(114 pages)
- Current page: 36 of 114
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15. Notes
This product is a stacked CSP package that a 64M (x16) bit Flash Memory and a 8M (x16) bit SRAM are assembled into.
- Supply Power
- Power Supply and Chip Enable of Flash Memory and SRAM (F-CE, S-CE
- Power Up Sequence
- Device Decoupling
Maximum difference (between F-V
S-CE
If the two memories are active together, possibly they may not operate normally by interference noises or data collision
on DQ bus.
Both F-V
data retention mode.
When turning on Flash memory power supply, keep F-RST “low”. After F-V
for more than 100nsec.
The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby
mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash
Memory. Note peak current caused by transition of control signals (F-CE, S-CE
1
should not be “low” and S-CE
CC
and S-V
CC
are needed to be applied by the recommended supply voltage at the same time expect SRAM
CC
2
and S-V
should not be “high” when F-CE is “low” simultaneously.
CC
L R S1 3 8 6
) of the voltage is less than 0.3V.
1
, S-CE
CC
2
1
)
reaches over 2.7V, keep F-RST “low”
, S-CE
2
).
34
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