lrs1805a Sharp Microelectronics of the Americas, lrs1805a Datasheet - Page 39
![no-image](/images/no-image-200.jpg)
lrs1805a
Manufacturer Part Number
lrs1805a
Description
Stacked Chip Flash Memory Smartcombo
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LRS1805A.pdf
(57 pages)
- Current page: 39 of 57
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14. Notes
This product is a stacked CSP package that a 64M (x16) bit Flash Memory and a 16M (x16) bit Smartcombo RAM are
assembled into.
- Supply Power
- Power Supply and Chip Enable of Flash Memory and Smartcombo RAM (F-CE, S-CE
- Power Up Sequence
- Device Decoupling
Maximum difference (between F-V
S-CE
If the two memories are active together, possibly they may not operate normally by interference noises or data
collision on DQ bus.
Both F-V
Smartcombo RAM data retention mode.
When turning on Flash memory power supply, keep F-RST low. After F-V
more than 100 nsec.
The power supply is needed to be designed carefully because one of the Smartcombo RAM and the Flash Memory is in
standby mode when the other is active. A careful decoupling of power supplies is necessary between
Smartcombo RAM and Flash Memory. Note peak current caused by transition of control signals (F-CE, S-CE
1
should not be low and S-CE
CC
and S-V
CC
are needed to be applied by the recommended supply voltage at the same time expect
2
CC
should not be high when F-CE is low simultaneously.
and S-V
L R S 1 8 0 5 A
CC
) of the voltage is less than 0.3V.
CC
reaches over 2.7V, keep F-RST low for
1
, S-CE
2
)
1
, S-CE
2
).
37
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